Tim 'mithro' Ansell

So, either; (a) the macros shouldn't be connected to the extra power rails and thus everything is fine (b) the macros should be connected to these extra power rails and...

@mkkassem

@mkkassem

The SHA1SUMs are for the output OAS / GDS file which is downloaded using the command. Take a look at https://github.com/mithro/mpw-tools

See specifically https://github.com/mithro/mpw-tools/blob/be3862b72dde6068e3e865cf89c1ea5e265743df/get-mpw-files.py#L79-L105 and https://github.com/mithro/mpw-tools/blob/be3862b72dde6068e3e865cf89c1ea5e265743df/get-mpw-files.py#L108-L126

FYI - The author of VexRISCV, @Dolu1990, might be interested in this thread.

@dlmiles / @RTimothyEdwards - Be careful here, VexRISCV is an extremely configurable CPU (https://github.com/SpinalHDL/VexRISCV#description) with a huge number of options which can be selected. It offers 2 stage to 5+...

BTW There was also a whole bunch of work to create a very fast, very low resource, XIP SPI module for LiteX inside https://github.com/litex-hub/litespi

@dlmiles - Apologize for the noise -- I was skimming the issue and wrongly concluded that "CPU is slow" was referring to "VexRISCV executing from XSPI" (there has been a...

Which SPI controller are you using? [LiteSPI supports](https://github.com/litex-hub/litespi) single/dual/quad/octal modes both [without DDR](https://github.com/litex-hub/litespi/blob/master/litespi/phy/generic_sdr.py) and [with DDR](https://github.com/litex-hub/litespi/blob/master/litespi/phy/generic_ddr.py). The [older `spi_flash.py` module](https://github.com/enjoy-digital/litex/blob/e17a01086666c86cfbcad9e8eb0efa3231a0fe8a/litex/soc/cores/spi_flash.py#L89) also supports Dual and Quad mode.