Tim 'mithro' Ansell comments

Results 1504 comments of


                                            Tim 'mithro' Ansell

Cleanup old branches?

@antonblanchard - Could you look at this?

DNM: Change URL for the theme.

Currently this makes the workshop ugly / not work properly.... ![image](https://github.com/im-tomu/fomu-workshop/assets/21212/ef7391cf-18b4-46f3-ac03-0d4abae30e9f)

Control/status registers

Couple of random thoughts; * Divorcing the CSRs from the bus they are implimented on sounds great. * Being able to output SVD format would be super awesome. * It...

I have no actual proof here, so it would be good for someone to do some real analysis rather than my anecdotes. There might be some useful information @ https://zipcpu.com/zipcpu/2019/08/30/subbus.html...

[Request] A proposal for CSRs

@xobs - FYI

export as hierarchy (verilog modules)

@jordens Are you actively working on this at the moment or is this something you would just like to see in the future?

Missing documentation for migen.genlib modules

FYI - @ajitmathew

construct and use sensitivity graph to speed up sim and find comb loops

FYI - @ishan98

Should Migen generate explicit Verilog for mismatched bit vector lengths (rather then relying on implicit Verilog behaviour?)

FYI - The DMA engine in LiteVideo has changed between absolute addressing and start of the DDR addressing at some point in the past.