Matt Guthaus
Matt Guthaus
PicoRV32!
Typically, designers would read in a black box Verilog file. There is a (slightly out of date) behavioral one available at: https://github.com/VLSIDA/OpenRAM/blob/master/compiler/tests/golden/sram_2_16_1_scn3me_subm.v
I did some more digging and all that I think needs to be added is: 1) support for busses in the Liberty file 2) ability to read in more than...
I tried rerunning everything with the debug enabled klayout, but it doesn't run into this problem. :(
Flattening isn't an option for large designs... the run-time after flattening would be impractical for a chip-level design (or even an IP level design). I'm not sure that it is...
I will try to integrate some of these changes later, but right now they are hacks rather than parameterized additions to the tech file. In general, we don't allow technology...
This is an issue that the PTM models from FreePDK45 aren't included by default. It can't find the models and so simulations fail with whatever default device models are in...
It shouldn’t but there could be instances where the power routing is difficult or characterization takes a long time. 256kb is getting big too for a single array but it...
That’s an unusually large word size so I’ll have to check that out. It could be a runtime bug in our channel router.
Hi David, How do you commit? If you do a "git commit -a" it will commit the .gitignore as well. You should go through and do a "git add "...