Matt Guthaus
Matt Guthaus
Yes, this is a duplicate of https://github.com/VLSIDA/OpenRAM/issues/228
inline_lvsdrc runs LVS and DRC at every hierarchical level instead of only at the end. You shouldn't turn this on for sky130 since the bitcells cannot pass on their own....
I would suggest that you get simulation working to verify a 200MHz operation.
The characterization model used won't change the layout and implementation. So both will result in the same design layout, but the .lib file with delay and power will be different.
The layer errors are complaining about necessary layers in the macro. These are for OPC etc and cannot be removed. On Fri, Jul 19, 2024, 02:52 K.Makise ***@***.***> wrote: >...
It's shown as an error, but it is really a warning.
Is that a question for me?
As far as I know, these are different than the published docker images. The current docker build script does not tag the image.
@povik Can you take a look? I think I've got general improvement in QoR in most cases.