Liberty memory support

[mguthaus]

The read_celllib command reads a cell library, but it does not recognize memories. These require support for busses and the memory cell type. You can see an example from OpenRAM at:

https://github.com/VLSIDA/OpenRAM/blob/master/compiler/tests/golden/sram_2_16_1_scn3me_subm_TT_5p0V_25C.lib

Let me know if you have any questions or if you have suggestions for adjusting memory lib files for use in OpenTimer.

[tsung-wei-huang]

Hi @mguthaus , can you point me to the verilog netlist file? Thanks!

[mguthaus]

Typically, designers would read in a black box Verilog file. There is a (slightly out of date) behavioral one available at:

https://github.com/VLSIDA/OpenRAM/blob/master/compiler/tests/golden/sram_2_16_1_scn3me_subm.v

[tsung-wei-huang]

@mguthaus Thank you for bringing this up to our attention. I will look into this and get you back soon!

[mguthaus]

I did some more digging and all that I think needs to be added is:

1. support for busses in the Liberty file
2. ability to read in more than one .lib and append The cell timing models are basically the same as DFFs.

[etch32]

Hi, I too am interested in memory .lib support (with busses). I'm curious if you will have time to look into this issue in the near future or if you have other priorities?

Thank you