Matt Guthaus
Matt Guthaus
Or can @maliberty take a look?
Cool comparison tool. It seems there is consistent finish__power__total and finish__design__core__area improvement in most designs (none got worse). This is expected since this is using downsizing to get improvement. finish__timing__setup__ws...
@povik Can you take a lok?
@povik Can you take a look again? I believe I fixed all prior issues. Results in setup slack are mixed tending to improved slack. But this is because the one...
> I see merge conflicts to resolve. Is this otherwise ready for testing? I rebased and pushed, but it fails clang-tidy due to the CI issues, I believe?
This PDK had many of the FEOL rules completed: https://github.com/laurentc2/SKY130_for_KLayout
I integrated them with a PDK similar to yours here: https://github.com/VLSIDA/chip-tutorials/blob/main/klayout/tech/sky130/drc/sky130A.drc
I also see some issues with removing files now: ``` /tmp/DependencyInstaller-orfs-4G9buw ~/orfs-upstream rm: remove write-protected regular file 'verilator/.git/objects/pack/pack-1bba8259082364fd9eca4c7d20c41d90086becd2.idx'? y rm: remove write-protected regular file 'verilator/.git/objects/pack/pack-1bba8259082364fd9eca4c7d20c41d90086becd2.rev'? y rm: remove write-protected regular...
It's an odd, and very large, word size. I'd consider banking or other optimization. Often this type of thing is just caused by a pin access problem, but you would...
Is this due to any updates to the clock propagation with clock gating? My 2 cents: 1) If isClock is set, the gate should be "optimized" by CTS. But I...