VLSIDA
Liberty updates for power char and bus deinjfiotn
This pull request contains 2 changes:
- Power characterization subtracts leakage from the total power measurements - 50x measured power over the last 2% of period is subtracted from total power measurement. gen_meas_power gets an additional 'leakage' parameter to indicate if this is a leakage-only measurement (in which case leakage is not subtracted) or not.
- Liberty bus definitions were inverted, i.e. it was din[0:7] instead of din[7:0]
I don't know who to not include the modified .gitignore in this pull request.
Hi David,
How do you commit? If you do a "git commit -a" it will commit the
.gitignore as well. You should go through and do a "git add
Matt
The .gitignore is an old mess I created - I thought, mistakenly, I had committed it accidentally, so I removed it from teh repo with one of my older commits. I then proceeded with a few more commits after that.
What I am thinking is since I get the .gitignore from your dev branch, I can add/track it in my branch, so when you pull my branch if should just do a noop on the .gitgnore?
-dave
On Jul 13, 2020, at 12:59 PM, Matt Guthaus [email protected] wrote:
Hi David,
How do you commit? If you do a "git commit -a" it will commit the .gitignore as well. You should go through and do a "git add
" for each file you want to commit. Then do a git commit to commit them all. Matt
On Mon, Jul 13, 2020 at 12:57 PM David R. [email protected] wrote:
This pull request contains 2 changes:
- Power characterization subtracts leakage from the total power measurements - 50x measured power over the last 2% of period is subtracted from total power measurement. gen_meas_power gets an additional 'leakage' parameter to indicate if this is a leakage-only measurement (in which case leakage is not subtracted) or not.
- Liberty bus definitions were inverted, i.e. it was din[0:7] instead of din[7:0]
I don't know who to not include the modified .gitignore in this pull request.
You can view, comment on, or merge this pull request online at:
https://github.com/VLSIDA/OpenRAM/pull/80 Commit Summary
- Remove file from tracking
- Fix voltage_map names (these do not need to match pg_pin names)
- Merge branch 'dev' of github.com:VLSIDA/OpenRAM into dev
- Merge branch 'dev' of github.com:VLSIDA/OpenRAM into dev
- Subtract leakage from total power measurement. Leakage is power for the last 2% of the period.
- Fix bus ordering in Liberty
File Changes
- D .gitignore https://github.com/VLSIDA/OpenRAM/pull/80/files#diff-a084b794bc0759e7a6b77810e01874f2 (12)
- M compiler/characterizer/delay.py https://github.com/VLSIDA/OpenRAM/pull/80/files#diff-f2b5d938f8790eded68e2dfa9ec12bec (2)
- M compiler/characterizer/lib.py https://github.com/VLSIDA/OpenRAM/pull/80/files#diff-34f6b2f3aef9758fca654912693337d3 (15)
- M compiler/characterizer/stimuli.py https://github.com/VLSIDA/OpenRAM/pull/80/files#diff-9765eb221da9dfb7d121ddbe35fd3e90 (23)
Patch Links:
- https://github.com/VLSIDA/OpenRAM/pull/80.patch
- https://github.com/VLSIDA/OpenRAM/pull/80.diff
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I pushed a new commit, which includes a merge of your dev branch, and the .gitignore. This should bring us at the same level, .gitignore wise.
I have also added the following additional enhancements:
- Fix for leakage subtraction from dynamic power measurements (removed the 50X factor)
- Added --num_threads command line option
- Modified POST=0 if purge_temp is True, else POST=1.
Hi David,
I'm seeing some regression issues with this contribution:
runTest (21_hspice_delay_test.timing_sram_test) ... ERROR: file testutils.py: line 151: NOT CLOSE disabled_write1_power -0.006 0.187 diff=103.1% ERROR: file testutils.py: line 151: NOT CLOSE write1_power 0.032 0.266 diff=87.8% ERROR: file testutils.py: line 151: NOT CLOSE write0_power 0.095 0.333 diff=71.5% ERROR: file testutils.py: line 151: NOT CLOSE read0_power 0.205 0.301 diff=31.8% ERROR: file testutils.py: line 151: NOT CLOSE disabled_write0_power 0.047 0.178 diff=73.7% ERROR: file testutils.py: line 151: NOT CLOSE read1_power 0.205 0.301 diff=31.7% ERROR: file testutils.py: line 139: Results exceeded 25.0% tolerance compared to golden results:
Also, the .lib results in the "golden" directory have changed. If the new ones are correct, can you update them with correct results? file1=/tmp/openram_gitlab-runner_18147_temp//sram_2_16_1_freepdk45_FF_1p0V_25C.lib file2=/home/gitlab-runner/builds/2fd64746/0/mrg/PrivateRAM/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib ERROR: file testutils.py: line 242: MISMATCH Line (64): downto : true; != } ERROR: file testutils.py: line 242: MISMATCH Line (65): } != ERROR: file testutils.py: line 242: MISMATCH Line (66): != type (addr){ ERROR: file testutils.py: line 242: MISMATCH Line (67): type (addr){ != base_type : array; ERROR: file testutils.py: line 242: MISMATCH Line (68): base_type : array; != data_type : bit; ERROR: file testutils.py: line 242: MISMATCH Line (69): data_type : bit; != bit_width : ; ERROR: file testutils.py: line 242: MISMATCH Line (70): bit_width : ; != bit_from : ; ERROR: file testutils.py: line 242: MISMATCH Line (71): bit_from : ; != bit_to : ; ERROR: file testutils.py: line 242: MISMATCH Line (72): bit_to : ; != } ERROR: file testutils.py: line 242: MISMATCH Line (73): downto : true; != ERROR: file testutils.py: line 242: MISMATCH Line (74): } != cell (sram____freepdk){
I will take care of these.
On Aug 3, 2020, at 1:59 PM, Matt Guthaus [email protected] wrote:
Hi David,
I'm seeing some regression issues with this contribution:
runTest (21_hspice_delay_test.timing_sram_test) ... ERROR: file testutils.py: line 151: NOT CLOSE disabled_write1_power -0.006 0.187 diff=103.1% ERROR: file testutils.py: line 151: NOT CLOSE write1_power 0.032 0.266 diff=87.8% ERROR: file testutils.py: line 151: NOT CLOSE write0_power 0.095 0.333 diff=71.5% ERROR: file testutils.py: line 151: NOT CLOSE read0_power 0.205 0.301 diff=31.8% ERROR: file testutils.py: line 151: NOT CLOSE disabled_write0_power 0.047 0.178 diff=73.7% ERROR: file testutils.py: line 151: NOT CLOSE read1_power 0.205 0.301 diff=31.7% ERROR: file testutils.py: line 139: Results exceeded 25.0% tolerance compared to golden results:
Also, the .lib results in the "golden" directory have changed. If the new ones are correct, can you update them with correct results? file1=/tmp/openram_gitlab-runner_18147_temp//sram_2_16_1_freepdk45_FF_1p0V_25C.lib file2=/home/gitlab-runner/builds/2fd64746/0/mrg/PrivateRAM/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib ERROR: file testutils.py: line 242: MISMATCH Line (64): downto : true; != } ERROR: file testutils.py: line 242: MISMATCH Line (65): } != ERROR: file testutils.py: line 242: MISMATCH Line (66): != type (addr){ ERROR: file testutils.py: line 242: MISMATCH Line (67): type (addr){ != base_type : array; ERROR: file testutils.py: line 242: MISMATCH Line (68): base_type : array; != data_type : bit; ERROR: file testutils.py: line 242: MISMATCH Line (69): data_type : bit; != bit_width : ; ERROR: file testutils.py: line 242: MISMATCH Line (70): bit_width : ; != bit_from : ; ERROR: file testutils.py: line 242: MISMATCH Line (71): bit_from : ; != bit_to : ; ERROR: file testutils.py: line 242: MISMATCH Line (72): bit_to : ; != } ERROR: file testutils.py: line 242: MISMATCH Line (73): downto : true; != ERROR: file testutils.py: line 242: MISMATCH Line (74): } != cell (sram____freepdk){
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There are still errors in the unit tests, but this may just be replacing the "golden" results with updated ones. I'll take a look at this soon.
Hi Prof Guthaus,
Yes, I will take care of those too.
-dave
Sent from my iPhone
On Sep 29, 2020, at 6:59 AM, Matt Guthaus [email protected] wrote:
There are still errors in the unit tests, but this may just be replacing the "golden" results with updated ones. I'll take a look at this soon.
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