circt
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llvm
Circuit IR Compilers and Tools
`circt/Support/Naming.h` contains heuristics for name picking, which are FIRRTL-specific. Extend this to allow it to work with multiple dialects.
On FIRRTL, there is a command-line flag (currently `--target:fpga`) that applies some transformations better suited to FPGA targets. Details are in https://github.com/chipsalliance/firrtl/blob/master/src/main/scala/firrtl/stage/FirrtlCompilerTargets.scala 1) Enable the [[firrtl.passes.memlib.InferReadWrite]] transform to reduce port...
This PR addresses issue #5681. When the new `inlineMemoryWrapperModules` is enabled, at the end HWMemSimImpl pass, it inlines the newly created memory wrapper modules and then removes them. Input FIRRTL...
Modify the LayerSink pass to compute and use the strongly connected components (SCCs) of FIRRTL operations to more aggressively sink operations into layerblocks. Fixes #6391. This is stacked on: #6491
When using `firtool` through Chisel 5.1.0 with the `--emit-chisel-asserts-as-sva` flag, assertions are always outputted as concurrent SVA properties. This is problematic for using with the free SymbiYosys verification toolchain, which...
Introduces the `circt-mc` tool that was previously drafted in #4647 - since there's a lot of bloat on that thread from development I figured a new PR for actual review...
This adds a connect op to the chirrtl dialect. this will be used for most of the connect weirdness, leaving firrtl.connect to handle sanely constrained IR.
Annotation resolution of aggregates of probes should produce a better error message. Currently, this fails to find the "name". The actual issue is that it is an annotation targeting a...
``` hw.module @Foo(in %a : i1) { %true = hw.constant true %r = sv.reg : !hw.inout sv.initial { %0 = comb.and %a, %true : i1 sv.passign %r, %0 : i1...
