[SV][LowerSeqToSV] MLIR verifier/parer stack overflow in constructing deeply nested if

[uenoku]

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IR lowered from following chisel has deeply-nested if operation with 2^14 depth. It causes stackoverflow in MLIR verifier (and parser if we use textual format of MLIR). Bytecode seems working.

//> using scala "2.13.10"
//> using lib "org.chipsalliance::chisel::5.0.0"
//> using plugin "org.chipsalliance:::chisel-plugin::5.0.0"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import circt.stage.ChiselStage
import chisel3.util.PriorityEncoder

class Foo(width:Int) extends Module {
  val input = IO(Input(UInt(math.pow(2, width).toInt.W)))
  val out = IO(Output(UInt(width.W)))

  val reg = RegInit(0.U(width.W))
  out := reg 
  reg := PriorityEncoder(input)
}

object Main extends App {
  println(
    ChiselStage.emitCHIRRTL(new Foo(14))
  )
}

foo.mlirbc.zip circt-opt foo.mlirbc or mlir-opt --allow-unregistered-dialect foo.mlirbc should reproduce the failure.

#743 0x0000000002ff45c3 mlir::LogicalResult::failed() const /scratch/hidetou/circt/llvm/mlir/include/mlir/Support/LogicalResult.h:44:33
#744 0x0000000002ff45c3 mlir::failed(mlir::LogicalResult) /scratch/hidetou/circt/llvm/mlir/include/mlir/Support/LogicalResult.h:72:58
#745 0x0000000002ff45c3 (anonymous namespace)::OperationVerifier::verifyDominanceOfContainedRegions(mlir::Operation&, mlir::DominanceInfo&) /scratch/hidetou/circt/llvm/mlir/lib/IR/Verifier.cpp:361:15
#746 0x0000000002ff45c3 mlir::LogicalResult::failed() const /scratch/hidetou/circt/llvm/mlir/include/mlir/Support/LogicalResult.h:44:33
#747 0x0000000002ff45c3 mlir::failed(mlir::LogicalResult) /scratch/hidetou/circt/llvm/mlir/include/mlir/Support/LogicalResult.h:72:58
#748 0x0000000002ff45c3 (anonymous namespace)::OperationVerifier::verifyDominanceOfContainedRegions(mlir::Operation&, mlir::DominanceInfo&) /scratch/hidetou/circt/llvm/mlir/lib/IR/Verifier.cpp:361:15
#749 0x0000000002ff45c3 mlir::LogicalResult::failed() const /scratch/hidetou/circt/llvm/mlir/include/mlir/Support/LogicalResult.h:44:33
#750 0x0000000002ff45c3 mlir::failed(mlir::LogicalResult) /scratch/hidetou/circt/llvm/mlir/include/mlir/Support/LogicalResult.h:72:58
#751 0x0000000002ff45c3 (anonymous namespace)::OperationVerifier::verifyDominanceOfContainedRegions(mlir::Operation&, mlir::DominanceInfo&) /scratch/hidetou/circt/llvm/mlir/lib/IR/Verifier.cpp:361:15
#752 0x0000000002ff45c3 mlir::LogicalResult::failed() const /scratch/hidetou/circt/llvm/mlir/include/mlir/Support/LogicalResult.h:44:33
#753 0x0000000002ff45c3 mlir::failed(mlir::LogicalResult) /scratch/hidetou/circt/llvm/mlir/include/mlir/Support/LogicalResult.h:72:58
#754 0x0000000002ff45c3 (anonymous namespace)::OperationVerifier::verifyDominanceOfContainedRegions(mlir::Operation&, mlir::DominanceInfo&) /scratch/hidetou/circt/llvm/mlir/lib/IR/Verifier.cpp:361:15
#755 0x0000000002ff45c3 mlir::LogicalResult::failed() const /scratch/hidetou/circt/llvm/mlir/include/mlir/Support/LogicalResult.h:44:33
#756 0x0000000002ff45c3 mlir::failed(mlir::LogicalResult) /scratch/hidetou/circt/llvm/mlir/include/mlir/Support/LogicalResult.h:72:58
#757 0x0000000002ff45c3 (anonymous namespace)::OperationVerifier::verifyDominanceOfContainedRegions(mlir::Operation&, mlir::DominanceInfo&) /scratch/hidetou/circt/llvm/mlir/lib/IR/Verifier.cpp:361:15

[uenoku]

An updated reproducer for 1.59.0

//> using scala "2.13.10"
//> using lib "org.chipsalliance::chisel::5.0.0"
//> using plugin "org.chipsalliance:::chisel-plugin::5.0.0"
//> using options "-unchecked", "-deprecation", "-language:reflectiveCalls", "-feature", "-Xcheckinit", "-Xfatal-warnings", "-Ywarn-dead-code", "-Ywarn-unused", "-Ymacro-annotations"

import chisel3._
import circt.stage.ChiselStage

class Foo(width:Int) extends Module {
  val depth = math.pow(2, width).toInt
  val cond = IO(Input(UInt(depth.W)))
  val out = IO(Output(UInt(width.W)))

  val reg = RegInit(0.U(width.W))
  out := reg
  for (i <- 0 until depth){
    when(cond(i)){
      reg := reg + i.U(width.W)
    }
  }
}

object Main extends App {
  println(
    ChiselStage.emitCHIRRTL(new Foo(14))
  )
}

[firtool] Running "externalize-clock-gate{enable=en input=in instance-name=ckg name=EICG_wrapper output=out test-enable=test_en}"
[firtool] -- Done in 0.002 sec
[firtool] Running "lower-seq-to-sv{disable-reg-randomization=false emit-separate-always-blocks=false lower-to-always-ff=true}"
PLEASE submit a bug report to https://github.com/llvm/circt and include the crash backtrace.
Stack dump:
0.      Program arguments: firtool foo.fir -verbose-pass-executions -o neko.sv
Stack dump without symbol names (ensure you have llvm-symbolizer in your PATH or set the environment var `LLVM_SYMBOLIZER_PATH` to point to it):
0  firtool         0x0000000000722b67 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) + 39
1  firtool         0x000000000072091e llvm::sys::RunSignalHandlers() + 238
2  firtool         0x000000000072349f
3  libpthread.so.0 0x00007f7f75b45cf0
4  firtool         0x00000000006d6c12 llvm::SmallPtrSetImplBase::SmallPtrSetImplBase(void const**, llvm::SmallPtrSetImplBase const&) + 2
5  firtool         0x0000000000fa6529 llvm::iterator_range<llvm::pointee_iterator<llvm::df_iterator<mlir::Block*, llvm::df_iterator_default_set<mlir::Block*, 8u>, false, llvm::GraphTraits<mlir::Block*>>, std::remove_reference<decltype(*(*std::declval<llvm::df_iterator<mlir::Block*, llvm::df_iterator_default_set<mlir::Block*, 8u>, false, llvm::GraphTraits<mlir::Block*>>>()))>::type>> llvm::make_pointee_range<llvm::iterator_range<llvm::df_iterator<mlir::Block*, llvm::df_iterator_default_set<mlir::Block*, 8u>, false, llvm::GraphTraits<mlir::Block*>>>&, llvm::df_iterator<mlir::Block*, llvm::df_iterator_default_set<mlir::Block*, 8u>, false, llvm::GraphTraits<mlir::Block*>>>(llvm::iterator_range<llvm::df_iterator<mlir::Block*, llvm::df_iterator_default_set<mlir::Block*, 8u>, false, llvm::GraphTraits<mlir::Block*>>>&) + 57
6  firtool         0x0000000000f9d943
7  firtool         0x0000000000faad63 mlir::WalkResult mlir::detail::walk<mlir::ForwardDominanceIterator<false>>(mlir::Operation*, llvm::function_ref<mlir::WalkResult (mlir::Operation*)>, mlir::WalkOrder) + 115
8  firtool         0x0000000000faafcf mlir::WalkResult mlir::detail::walk<mlir::ForwardDominanceIterator<false>>(mlir::Operation*, llvm::function_ref<mlir::WalkResult (mlir::Operation*)>, mlir::WalkOrder) + 735
9  firtool         0x0000000000faafcf mlir::WalkResult mlir::detail::walk<mlir::ForwardDominanceIterator<false>>(mlir::Operation*, llvm::function_ref<mlir::WalkResult (mlir::Operation*)>, mlir::WalkOrder) + 735
10 firtool         0x0000000000faafcf mlir::WalkResult mlir::detail::walk<mlir::ForwardDominanceIterator<false>>(mlir::Operation*, llvm::function_ref<mlir::WalkResult (mlir::Operation*)>, mlir::WalkOrder) + 735
11 firtool         0x0000000000faafcf mlir::WalkResult mlir::detail::walk<mlir::ForwardDominanceIterator<false>>(mlir::Operation*, llvm::function_ref<mlir::WalkResult (mlir::Operation*)>, mlir::WalkOrder) + 735
12 firtool         0x0000000000faafcf mlir::WalkResult mlir::detail::walk<mlir::ForwardDominanceIterator<false>>(mlir::Operation*, llvm::function_ref<mlir::WalkResult (mlir::Operation*)>, mlir::WalkOrder) + 735
13 firtool         0x0000000000faafcf mlir::WalkResult mlir::detail::walk<mlir::ForwardDominanceIterator<false>>(mlir::Operation*, llvm::function_ref<mlir::WalkResult (mlir::Operation*)>, mlir::WalkOrder) + 735