Teguh Hofstee

> T motors have a good reputation, in their GB line they say that the motors have little cogging, but I found a video on youtube where you can see...

> 1. Give you much better resolution (more steps per rotation of the knob thanks to gearing) Magnetic encoders will already get you

Doesn't verilator have issues with double underscores in names? Try removing all consecutive underscores and seeing if that helps.

Notably, I just want to recompile the VCS testbench I'm using and run `./simv` manually myself.

I believe it's pyverilog parsing. I'm not entirely sure how/when magma processes the AST but it wasn't showing up in my profiling. If the conversion of the AST to magma...

If we're doing shallow parsing, we only need the modules specified in the `target_modules` right? So can't you just do something like ``` for mod in target_modules: magma.DefineFromVerilog(re.search(f"module {mod} \([^)]*\);(?s)*?endmodule"))...

Except wiring is _not_ structural, because I can't wire `Bit` to `Bits[1]`.

I'd also second the option to just be able to truncate some stuff off the start and end. The lines at the start and the end can't be aligned to...

Here's the first few lines of the generated code: ``` mod __gl_imports { pub use std::mem; pub use std::os::raw; } #[inline(never)] fn metaloadfn(mut loadfn: &mut FnMut(&str) -> *const __gl_imports::raw::c_void, symbol:...

After looking through the maze of code from Garnet through Gemstone, Mantle, Magma, and back to CoreIR, this is what I think needs to happen: [`include/coreir/definitions/coreVerilog.hpp`](https://github.com/rdaly525/coreir/blob/master/include/coreir/definitions/coreVerilog.hpp) needs to be modified...