Teguh Hofstee
Teguh Hofstee
The SystemVerilog targets actually don't compile the Verilog testbench unless you call `compile_and_run` instead of just `compile`.
If you wire the clock parameter to a testbench, I would assume that it works without having to do anything special to the clock. However fault does not initialize the...
Refiling here instead of other repo. Sorry if it's a duplicate. Specifically, I'm looking to mimic the following SystemVerilog code: ```systemverilog always_ff @(posedge clk, negedge rst_n) if (~rst_n) q
For a 32x16 CGRA (~1MB Verilog file), it takes over 90 seconds to get through the parse step of magma. I really only want the top `Garnet` module's interface to...
I'm seeing this warning on rust nightly: ``` warning: variable does not need to be mutable --> out/gl_bindings.rs:9:23 | 9 | fn metaloadfn(mut loadfn: &mut FnMut(&str) -> *const __gl_imports::raw::c_void, |...
When using the clock-gated registers output by CoreIR, the synthesis tools do not recognize this and put a correctly clock-gated register cell in the design. @mbstrange2 has more details. In...
Is there a pass to remove passthrough modules? I'm seeing 1-input muxes in the post-synthesis netlists, and while this technically isn't illegal it's causing warnings in tools and ideally, I'd...
If you pull my repo and run ``` make rigel luajit examples/conv.lua 1 32 ``` it generates the following error. I think it's because it's trying to change a broadcast(32,32)...
**Describe the bug** `mise` doesn't appear to be respecting the `sources` and `outputs` to skip running a task. **To Reproduce** I have this in my `mise.toml` ```toml [tasks.bundle_id] sources =...
`layer_switch` exists in `action.h` but is not actually implemented anywhere.