tester.compile doesn't recompile VCS

[hofstee]

The SystemVerilog targets actually don't compile the Verilog testbench unless you call compile_and_run instead of just compile.

[hofstee]

Notably, I just want to recompile the VCS testbench I'm using and run ./simv manually myself.

[leonardt]

Makes sense, I think this feature (compile) was added for verilator but never ported for the SV targets