ghdl-yosys-plugin
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ghdl
VHDL synthesis (based on ghdl)
This PR aims to improve the makefiles of the example projects. The goal is to make the examples easier to understand, use and maintain. **Changes**: - Created a `tools.mk` file...
When I try to process a test entity instantiating a `scfifo` from the `altera_mf` library I get this error. ERROR LOG: ``` ghdl --std=08 -P=altera/ -fsynopsys test.vhdl -e test 1....
I declare an entity which has an `inout record` port. When I run simulation in GHDL, it works as intended. When I try to run it through yosys I get...
yosys -m ghdl -p "ghdl --std=93c --ieee=synopsys -fexplicit -Whide -Wspecs dut2; write_cxxrtl blink.cpp" /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia...
``` library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity blink is port ( clk : in std_logic; inp : in std_logic_vector(63 downto 0); ou : out std_logic_vector(63 downto 0) ); end...
I am testing to see if I can blackbox modules and just test the wiring connections between them. So there are a few issues. The source code has import statements...
Is their is a way to see report statment and the current state by name. Because cxxrtl ignore the report statment and convert all state into binary.
Hello, I installed `mingw-w64-x86_64-yosys` package from the `mingw-w64-x86_64-eda` package group via MSYS2 on my Windows 10 machine as recommended in the readme. When I try to show a schematic view...
CXXRTL allows for blackboxes, that are implemented by C++ code during the simulation. To do this in Verilog, the module is marked up as follows: ``` (* cxxrtl_blackbox *) module...
hello, i have also noticed that debug messages (for example writeline) from vhdl sources are not printed to the console during simulation with cxxrtl is there any way to see...
