ghdl-yosys-plugin

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Add analysis support

7

This change allows us to run ghdl analysis without having to exit from yosys

LAK132

Use of BRAM in ICE40 ...

2

Dear, can anyone help me using BRAM 512 word, 16 bit as a ROM (RAM preloaded during FPGA power on) using GHDL VHDL -> Yosys -> Lattice ICE40 FPGA please...

PPlinux

High impedance assignment translates to 1'x

6

When trying to assign a pin to HiZ I get a hard low drive instead. Reproducer below. I dub this bug "resisting high impedance" :) ent.vhdl: ``` library ieee; use...

DanielG

VHDL to Verilog conversion with yosys-ghdl-plugin -- how to perserve signal names

4

I have this **VHDL** design in a file `spi_icebreaker.vhdl`: -- A: library ieee; use ieee.std_logic_1164.all; -- B: entity spi_icebreaker is port( pcb_oscilator: in std_logic; pcb_led: out std_logic; pcb_button: in std_logic...

71GA

Error building ghdl plugin for yosys

14

First I cannot build ghdl locally, so I use the latest release from [fpga-tool-chain](https://github.com/YosysHQ/fpga-toolchain). And I am able to run binary `ghdl`, but when I try to build ghdl plugin...

minghunghw

Another case of "wire not found for $posedge" - related to async resets?

3

I'm not sure whether or not this is related to the existing issues which mention this error message, but I have a testcase which I hope will be useful. I'm...

robinsonb5

[WIP] Implement a VHDL backend

9

This will be a VHDL backend from #112, and I will be using this PR to track what has been finished and what still needs work. - [ ] Adjust...

rlee287

Roadmap for a release

1

Is there a Roadmap for a release of this project ? I'm using it intensively for Verilog conversion in conjunction with verilator to boost simulation performance. I'm also using it...

Martoni

Upload of ghdl-yosys-plugin to Debian?

5

Hello, both ghdl and yosys are in Debian, but to the best of my understanding this connective plugin is not. Would this be supported from your side? While I could...

smoe

wire not found for $posedge

3

Hi, I'm not sure if this is a duplicate of #110, #128 (supposedly fixed?) or #146, but I'm pretty sure this code (which implements a pipelined SIPO) should be perfectly...

kammoh