ghdl-yosys-plugin
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ghdl
VHDL synthesis (based on ghdl)
As commented in https://github.com/tgingold/ghdlsynth-beta/pull/78#issuecomment-575269066, currently some tests print a single green "OK" when successful. Other tests print an additional white "OK" before the green one. As shown in https://github.com/tgingold/ghdlsynth-beta/commit/910073d647e55d133494429d8c3a4bacffc32428/checks?check_suite_id=408343766#step:3:1619, `ghdl-issues/issue1000`,...
Currently the source location data present in GHDL is not preserved when creating a Yosys netlist. This PR adds the `/src` attribute to every cell when present in GHDL. Note...
Hi Tristan, Thanks again for the fixes to the demux. That has allowed us to take a look at both ilang and verilog dumps from Yosys. I would like to...
While building the plugin via "make", I was getting the following error. ``` src/ghdl.cc:760:8: error: use of undeclared identifier 'Id_Dlatch'; did you mean 'Id_Latch'? case Id_Dlatch: ^~~~~~~~~ Id_Latch /usr/local/include/ghdl/synth_gates.h:72:4: note:...
Under prebuilt tools you point to [open-tool-forge/fpga-toolchain](https://github.com/open-tool-forge/fpga-toolchain), please note that project now says it is no longer being maintained or updated
I've been using the workflow described in this link https://vhdlwhiz.com/formal-verification-in-vhdl-using-psl/#yosys-et-al It has afforded me great success, and i've taken my first steps with formal verification with PSL and GHDL. However,...
Both Yosys and GHDL work fine, but when compiling the VHDL code I always get the same error: ``` dyld[69836]: missing symbol called ``` I have tried using it along...
Completely different code for the other issue with the same title, so a separate issue. At least this one is nice and minimal. ```vhdl library ieee; use ieee.std_logic_1164.all; entity test...
Original project: https://cryptography.gmu.edu/athena/sources/2012_03_23/Keccak/without_padding/Keccak_PPL.zip Attached in the zip, the modified version with comments. We tried to circumvent some issues by modifying the VHDL code. Ideally we would like to use this...
https://github.com/open-tool-forge/fpga-toolchain points to https://github.com/YosysHQ/fpga-toolchain, which was archived on Nov 2021.
