Enable cxxrtl blackboxes in vhdl by propagating attributes of entity

[david-sawatzke]

CXXRTL allows for blackboxes, that are implemented by C++ code during the simulation. To do this in Verilog, the module is marked up as follows:

(* cxxrtl_blackbox *)
module test (
(* cxxrtl_edge ="p" *) input wire clk;
input wire rst
);
// Empty

endmodule

I would expect a this to look akin to the following in VHDL:

library ieee;
use ieee.std_logic_1164.all;

entity test is
  port (
    clk_i     : in  std_ulogic;
    rstn_i    : in  std_ulogic
  );
  -- Define the custom attributes
  attribute blackbox : boolean;
  attribute blackbox of test : entity is true; -- Apply the blackbox attribute
  attribute cxxrtl_blackbox : boolean;
  attribute cxxrtl_blackbox of test : entity is true;
  attribute cxxrtl_edge : string;
  attribute cxxrtl_edge of clk_i : signal is "p"; -- Apply the edge attribute to clk_i
end test;

architecture test_rtl of test is

begin
  --black box implementation
end test_rtl;

but all of these attributes are discarded in the rtlil (the ones for the entity with a warning for unkept-attribute), thus not resulting in any blackbox.

This is probably related to https://github.com/ghdl/ghdl/issues/2675.

Is there a way around this (by e.g. setting these attributes in yosys?) until they are propgated or a better way to write it in VHDL?