ghdl-yosys-plugin

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Mixed synthesis with a Verilog top-level fails when parameters are specified

2

Hi. We (@eine) were testing mixed synthesis cases. * Verilog + VHDL (top) works (note: the Verilog module must be specified as component into the VHDL). * VHDL + Verilog...

rodrigomelo9

Add support for Yosys $live cell (needed for liveness proofs)

2

I've done some tests with liveness proofs using PSL properties like: ```vhdl assert always (rose(a) -> eventually! b); ``` I noticed that such constructs are processed by GHDL (and Yosys),...

tmeissner

ERROR: wire not found for $posedge

3

I've got a relatively simple code example with abnormal style which doesn't synthesize: ``` vhdl library IEEE; use IEEE.std_logic_1164.all; entity lfsr2 is port( clk : in std_logic; reset : in...

stevenbell

"ERROR: wire not found for $posedge" when synthesizing dynamic array insertion

12

- ghdl/ghdl@8789de96 - ghdl-yosys-plugin 6ef4d46 - YosysHQ/yosys@3cb3978ff The following file: ```vhdl :file: ent.vhd library ieee; use ieee.std_logic_1164.all, ieee.numeric_std.all; entity ent is port ( clk : in std_logic; y : out...

Xiretza

GHDL synth internal state inconsistent with Yosys state

6

(The title of this issue refers to my best guess at explaining the behavior below, as I have not dived into how the GHDL synthesis code actually works. Please let...

rlee287

Multiple use of module

2

**Description** ghdl or yosys changes module port names to lowercase **Expected behaviour** I want to use the module (i.e. entity) mux2_1 in mux4_1 and mux4_1_x2. Using ``` ghdl mux2_1.vhd -e...

IIupor

Testing on some designs from Opencores

4

Used msys2 32bit in Windows 7 to integrate everything together. I've compiled ghdl 81905a8c. Then used ghdl-yosys-plugin 0b687cd. In-compiled it directly into the yosys 334ec5fa. [fails.zip](https://github.com/ghdl/ghdl-yosys-plugin/files/4797482/fails.zip) I hope this will...

Chopper455

Feature suggestion: add a `ghdl_write_vhdl` command to yosys through the plugin

5

This would greatly help with simulating mixed-language projects, which could look like the following: Verilog testbench (which should be possible now): 1. Use yosys to synthesize the modules (which may...

rlee287

Improve conversion of records

3

Hi Tristan ! So I'm trying to use a ghdl+yosys conversion of microwatt to verilog in order to be able to simulate it in the LiteX environment. The end result...

ozbenh

Tighter integration with Yosys

15

I just thought it'd be good to have a place to keep track of how far removed we are from being able to upstream this project into Yosys, assuming they...

pepijndevos