Roadmap for a release

[Martoni]

Is there a Roadmap for a release of this project ? I'm using it intensively for Verilog conversion in conjunction with verilator to boost simulation performance. I'm also using it for formal verification and PSL support. But since there is no release, can we rely on it for «big» projects ?

So thanks again for this wonderful tool !

[umarcor]

I'm using it intensively for Verilog conversion in conjunction with verilator to boost simulation performance.

Note that ghdl synth --out=verilog allows converting VHDL to Verilog without requiring Yosys. See http://ghdl.github.io/ghdl/using/Synthesis.html#cmdoption-ghdl-out.

Is there a Roadmap for a release of this project ?

The complexity of versioning this plugin is the tight dependency on the versions of Yosys and GHDL. See:

• #74
• #162

But since there is no release, can we rely on it for «big» projects ?

This plugin is used in to generate ASICs for the Google/Skywater/efabless shuttles: https://efabless.com/open_shuttle_program/. See Anton Blanchard - Microwatt: a 64 bit OpenPOWER core, VHDL and OpenLANE..

I would not consider it to be proven for professional use yet. However, it can handle projects as large as you need to. On the other hand, the VHDL 2008 feature support is better than some professional vendor tools. See also:

• CHIPS Alliance Announces Xilinx as its Newest Member
• chipsalliance/fpga-interchange-schema
• chipsalliance/python-fpga-interchange