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Published 20 hours ago • verified publisher icon ghdl

Use of BRAM in ICE40 ...

Open PPlinux opened this issue 2 years ago • 2 comments

Dear,

can anyone help me using BRAM 512 word, 16 bit as a ROM (RAM preloaded during FPGA power on) using GHDL VHDL -> Yosys -> Lattice ICE40 FPGA please ?

Greetings,

Patrick

PPlinux avatar Jan 08 '22 14:01 PPlinux

I am new to the toolchain and am having trouble understanding how the techmap works in the plugin.

I have two entities, one is designed to be ROM while another as RAM. The ROM was mapped to BRAM while the RAM to DFFs.

I have no idea how to change this. Can anyone give some hints?

Thanks in advance.

kevingoh avatar Jul 21 '22 10:07 kevingoh

There is no ROM in an fpga, so it is expected that a ROM is mapped to a BRAM. If you RAM is not correctly described as a RAM, the synthesizer will use DFFs to implement it.

tgingold avatar Jul 22 '22 17:07 tgingold