f4pga-arch-defs
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f4pga
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Bumps [third_party/litex-boards](https://github.com/litex-hub/litex-boards) from `ea58ef9` to `19bce66`. Commits 19bce66 Add initial LimeSDR XTRX Platform support (Adapted from Fairwaves XTRX). 7a0ee7f platforms/fairwaves_xtrx: Change rst to rst_n (active low). 5a25a4e alinx_axau15p: Switch to...
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Bumps [third_party/liteeth](https://github.com/enjoy-digital/liteeth) from `150710d` to `e209a1c`. Commits e209a1c Merge pull request #160 from whiteb3ar/master 0e8079a phy/ecp5rgmii.py: In-Band Status CSRField("clock_speed") size fixed a0d59dd frontend/stream/LiteEthStream2UDPTX: Condition source.last_be to source.last. 79ccffc mac/crc: Revert...
In the current artix7 architecture, when using the falling edge of a clock such as negedge clk, due to the lack of clk reverse mux in the slice of arch.timing.xml,...
I wanted to write a controller for the qspi flash on the Nexys 4 DDR / Nexys A7. To do that i need to instantiate a STARTUPE2 primitive to control...
Bumps [third_party/litedram](https://github.com/enjoy-digital/litedram) from `2c60861` to `7dacfaf`. Commits 7dacfaf Merge pull request #352 from maribu/litedram/phy/lpddrX/commands.py/fix-inval... d6bf987 Merge pull request #354 from hansfbaier/downconvert-cleanup d7344c0 frontend/avalon: Remove downconvert specific logic (no longer required...
Bumps [third_party/litex-boards](https://github.com/litex-hub/litex-boards) from `ea58ef9` to `6a7c908`. Commits 6a7c908 Merge pull request #586 from litex-hub/xilinx_zcu106_fmc 11956b1 platforms/xilinx_zcu106.py: added connectors and FMC HPC0/1 c660a7a Merge pull request #585 from hansfbaier/qmtech-fgg676-fix f544fec Merge...
Bumps [third_party/litex](https://github.com/enjoy-digital/litex) from `95b310e` to `10083f4`. Commits 10083f4 Merge pull request #1958 from nrndda/patch-1 2d52c65 Simple mistake fix 4b3f147 CHANGES: Update. d5f9d57 Merge pull request #1956 from enjoy-digital/zynqmp_aximaster_eth_i2c_uart 943c0c2 soc/cores/cpu/zynqmp/core.py:...
Bumps [third_party/liteiclink](https://github.com/enjoy-digital/liteiclink) from `bba716a` to `f492a65`. Commits f492a65 bench/serwb/ti60_f225_dev_kit: Integrate SERIO for tests. 5a98f2e bench/serwb/demo: Demonstrate use of multiple SERIOs over the same link. 620e6c6 serwb/core: Make Downstream/Upstream arbitration more...
Bumps [third_party/migen](https://github.com/m-labs/migen) from `ccaee68` to `4790bb5`. Commits 4790bb5 Updated EEM FMC Carrier platform for v1.1 50934ad pyproject.toml: add build backend fd0bf58 doc: update installation instructions ecc1efe doc: fix URLs 3ba41c0...
Bumps [third_party/litex](https://github.com/enjoy-digital/litex) from `95b310e` to `0af1ae8`. Commits 0af1ae8 soc/cores/cpu/zynqmp/core.py: added add_gpios method to connect EMIO to the P... 44d049f litex/soc/integration/soc.py: add_uart: disable check_duplicate -> required w... 14dbdeb soc/integration/export: Disable fields_access_function...