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FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

Results 159 f4pga-arch-defs issues
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Bumps [third_party/litedram](https://github.com/enjoy-digital/litedram) from `2c60861` to `e9adaeb`. Commits e9adaeb setup.py: Fix/Revert classifiers. 8ed232f setup.py: Bump to 2023.12 to prepare release. b55cd3d setup.py: Switch minimum Python version to 3.7 (To allow more...

dependencies
third-party

IP Core could be supported?

I've basically added arty s7 board by extending [what @liibin has done for ax7050](https://github.com/f4pga/f4pga-arch-defs/pull/2658) and the counter example worked just fine. After copying the newly generated arty s7 pinmap, which...

Bumps [third_party/migen](https://github.com/m-labs/migen) from `ccaee68` to `50934ad`. Commits 50934ad pyproject.toml: add build backend fd0bf58 doc: update installation instructions ecc1efe doc: fix URLs 3ba41c0 platforms/quickfeather: fix incorrect use of 'is' aadc19d zc706:...

dependencies
third-party

Bumps [actions/checkout](https://github.com/actions/checkout) from 3 to 4. Release notes Sourced from actions/checkout's releases. v4.0.0 What's Changed Update default runtime to node20 by @​takost in actions/checkout#1436 Support fetching without the --progress option...

dependencies
github_actions

Bumps [actions/upload-artifact](https://github.com/actions/upload-artifact) from 3 to 4. Release notes Sourced from actions/upload-artifact's releases. v4.0.0 What's Changed The release of upload-artifact@v4 and download-artifact@v4 are major changes to the backend architecture of Artifacts....

dependencies
github_actions

Bumps [third_party/pythondata-cpu-vexriscv](https://github.com/litex-hub/pythondata-cpu-vexriscv) from `a36d99e` to `03d8c47`. Commits 03d8c47 Merge pull request #20 from lschuermann/dev/pmp-plugin-switch 1aead15 Update built Verilog targets 63430af Add pmpAddressMatchingModes switch to select {PmpPlugin,PmpPluginNapot} c36b1f3 Update VexRiscv to...

dependencies
third-party

in some cases, the last edges can't be written into the "channels.db" file

Designs with latches fail in VPR with the following error: ``` Message: Failed to find matching architecture model for 'LDCE' ``` We should emit LDCE_ZINI into blif for the above...