f4pga-arch-defs
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build(deps): bump third_party/liteeth from `150710d` to `e209a1c`
Bumps third_party/liteeth from 150710d
to e209a1c
.
Commits
e209a1c
Merge pull request #160 from whiteb3ar/master0e8079a
phy/ecp5rgmii.py: In-Band Status CSRField("clock_speed") size fixeda0d59dd
frontend/stream/LiteEthStream2UDPTX: Condition source.last_be to source.last.79ccffc
mac/crc: Revert 30e66a7 (introducing a regression).421e008
mac/crc: Cosmetic cleanup.fb407ce
core/ip/LiteEthIPTX: Enable buffer to ease timings on checksum.b5d7ba1
core/udp: Revert TX/RX Buffer since not helping (at least for now).211cdc2
core/ip: Add optional input buffer on LiteEthIPTX to improve timings.30e66a7
mac/crc/LiteEthMACCRC32: Avoid multiple XORs/Checks on output.3e81039
mac/crc/LiteEthMACCRC32Inserter: Switch crc_packet/last_be to reset_less for ...- Additional commits viewable in compare view
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