f4pga-arch-defs
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build(deps): bump third_party/litex from `95b310e` to `0af1ae8`
Bumps third_party/litex from 95b310e
to 0af1ae8
.
Commits
0af1ae8
soc/cores/cpu/zynqmp/core.py: added add_gpios method to connect EMIO to the P...44d049f
litex/soc/integration/soc.py: add_uart: disable check_duplicate -> required w...14dbdeb
soc/integration/export: Disable fields_access_function by default.0503099
soc/integration/export: Add LITEX_CSR_ACCESS_FUNCTIONS/LITEX_CSR_FIELDS_ACCES...5b297f5
soc/integration_export: Split C header generation by sections.4502edd
soc/integration/export: Prepare split of C header generation in sections.10083f4
Merge pull request #1958 from nrndda/patch-12d52c65
Simple mistake fix4b3f147
CHANGES: Update.d5f9d57
Merge pull request #1956 from enjoy-digital/zynqmp_aximaster_eth_i2c_uart- Additional commits viewable in compare view
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