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enjoy-digital
Build your hardware, easily!
Commit Message: Enables CPUs to know which memory addresses are accessible via the connected memory_bus. Explanation: Current situation around the NaxRiscv: - `litex_sim --cpu-type naxriscv` working - `litex_sim --cpu-type naxriscv...
If the toolchain is a hosted one, it may have fortification turned on by default. Make sure to turn it off so that we don't end up with undefined references...
### Issue When using a small SRAM of 2048 bytes it is not possible to boot from SD card. The boot process will just get stuck without any error output....
Hi, I am using digilent_nexys4.py. I have used litescope to look at self.main_ram.bus.adr. This address is sent, unmodified, to the CellularRam on the board. But the ram only delivers a...
Currently it generates SVD with the following content: ```xml ... ... ``` It would be nice to be able to not include the data since it inconvenient for version control...
I am trying to add new commands in the demo main code and then run it it gives me: > /home/fathymd/litex2/riscv64-unknown-elf-gcc-8.3.0-2019.08.0-x86_64-linux-centos6/bin/../lib/gcc/riscv64-unknown-elf/8.3.0/../../../../riscv64-unknown-elf/bin/ld:`_ demo.elf section `.data' will not fit in region `sram'...
All toolchains classes have more or less the same structure / logic with most of the logic residing into `build` method. It may summarise by: 1. directories creation 2. finalize...
It would be great to be able to trace Signals by putting python annotations on them and have litescope automatically collect the signals with annotations to trace them
When trying to boot Rocketchip from the sdcard on the stlv-7325 board I get stuck on lift-off. Using Vexriscv and the stlv-7325 board I can get sdcardboot to work at...
