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enjoy-digital
Build your hardware, easily!
Hi there, I'm trying to test the CVA6 in my Nexys4 DDR board. Unfortunately I don't have a Genesys2 board. Basic simulation seems to work without issues, but running on...
I am trying to integrate the LiteSPI core as a flash controller to be accessible to a host through LitePCIe. I do not want to map the entire flash region...
Does anyone have any thoughts on the value of creating a PR that disables interrupts in the bios before it begins serial booting and downloading files via serial? I am...
I am trying to generate the example design using the openXC7 toolchain for a Kintex-7 based Genesys2 for which the toolchain option to the litex-boards target file has been kindly...
Hi, I wanted to understand how Litex actually creates the memory files using Migen. I wanted to compile my own C codes and be able to use the created binary....
The following code: [litex](https://github.com/enjoy-digital/litex/tree/master)/[litex](https://github.com/enjoy-digital/litex/tree/master/litex)/[soc](https://github.com/enjoy-digital/litex/tree/master/litex/soc)/[cores](https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores)/[spi](https://github.com/enjoy-digital/litex/tree/master/litex/soc/cores/spi) /spi_master.py Contains: ```("``0b1``", "Manual operation (CS handled by User, direct recopy of ``sel``), useful for Bulk transfers.")``` One would assume that one could now simply set...
- Added --depth 1 option to reduce clone time. - Added -b option to reduce clone time.
Hi, I didn't found a clean way for the CPU core.py to provide a reset (comming from its jtag debug module) to the SoC Here is what i mean as...
 I tried to use romBoot to run the demo on the Sipeed 138k, but it gets stuck at "liftoff." There are no more build options that I have selected,...
Allows to send arbitrary SPI CMDs to the FLASH. Examples (depending on flash chip): - flash_transfer_cmd 0x9F 0x00 0x00 0x00 -> Read ID reg - flash_transfer_cmd 0x06 0x01 0x00 ->...
