litex

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Is there any "hello world" example of partial reconfiguration / ICAP use? LiteX has a core for that (https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/icap.py) but I'd would be interested on any real use of it,...

suarezvictor

litex_sim does not reach the end of simulation with cv32e41p

4

Hello @enjoy-digital, I want to simulate the bare metal demo application on RISC-V cv32e41p and I had this bug of no prompt response. However, it works fine with the cv32e40p...

HugoDesneux

@enjoy-digital It is fine for me if you don't want to merge this. The user base might be very small, but I found it helpful.

cklarhorst

Question on SPI Flash Boot

3

LiteX Devs, We are looking at the linux-on-litex-vexriscv design for a project. So far the litex tools an ecosystem and the overall design has exceeded my expectations on every level....

finchlt

jevinskie

liteeth: Add DMA interface

2

sergpolkin

jevinskie

ClockFrequency() to get/set the frequency of a domain or signal

1

`ClockFrequency(cd_or_signal="sys", set_freq=None)` Can be used to verify correctness parameters like with the Intel chip ID functionality that specifies the clock should be 100e6: logging.warn(f"Altera Chip ID block should be clocked...

jevinskie

Add get_signals function (w/ optional recursion) for litescope usage

1

Useful for collecting signals for litescope: e.g. `analyzer_signals = [*get_signals(self.usb, recurse=True)]`

jevinskie

cores/video: new VideoTextGrid component

5

The VideoTextGrid is similar to the VideoTerminal, but instead of receiving a stream of characters from an attached UART, it exposes a csr (YXAC) to allow direct access to the...

swetland