async_fifo
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20 hours ago •
dpretet
dpretet
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
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Instead of doing the SystemVerilog trick that I described earlier, I define one more addition registers [wbinnextpt1](https://github.com/joeldushouyu/async_fifo/blob/cast-parameter/rtl/wptr_full.v#L24), similar for rpt_empty. Thus, I believe the code could still be keep in...
