Naoya Hatta

I wonder wether the following types should be distinguished as different types. Normalizing them to `Module55I::` may be required? ```systemverilog Module55I::; Module55I::; Module55I::; Module55I::; ```

I agree introducing delay notation like `#10;`, as minimal support for native test description, is not so difficult. But I concern that once it is introduced, more and more syntex...

> What kind of syntax are you referring, operations for file io and such? For example, `task`, `clocking`, constrainted random, sequential assertion and so on. About this point, maybe, we...

I don't have complete idea yet, the current image is like below: ```systemverilog #[test(half_adder)] module test () { #[clock(10, 10)] var clk: clock; #[reset(0, 5)] var rst: reset; var a:...

> `#[clock(10, 10)]` defines the clock duty cycle, and `#[reset(0, 5)]` defines a reset event, active high, with a length of 5? Yes. I intended it. Unbalance duty is not...

I have another idea about native Veryl tests. The detailed information is here: https://zenn.dev/dalance/articles/d451090305688f (It is written in Japanese, please use a translator) The summary is below: * Introducing test...

Hi, @mgeisler , @qwandor , #284 was already merged, so we can use mdbook 5.0 if new version (may be 0.4.0?) is released. Is there any plan for new release?

This separation is semantic change about behavior during reset, so I think it should be shown syntactically. SV and Veryl follows the rule "In the condition which a register is...

According to Formal syntax of LRM, `localparam` can take `unpacked_dimension` only, so `[]` can't be used. ``` local_parameter_declaration ::= localparam data_type_or_implicit list_of_param_assignments list_of_param_assignments ::= param_assignment { , param_assignment } param_assignment...

For example, Synopsys Formality outputs syntax error to this code. A purpose of sv-parser is detecting such corner cases (almost all tools work fine, but some tools don't) by implementing...