Naoya Hatta

I think this case should be reported as unused.

Probably, this feature can be realized after #1847, because all instantiation, generate, function are expanded in IR construction phase. #1287 will generate DAG of variables to decide evaluation order, so...

Now I'm working on #2005. First of all, I would like to replace unassignment and multiple-assignment check by IR-based. Probably this IR is useful for #1287.

> Can IR check [#788](https://github.com/veryl-lang/veryl/issues/788) ? Yes, probably.

OK. I'll add the following warnings, not error. ``` Warning: invalid_logical_operand (https://doc.veryl-lang.org/book/07_appendix/02_semantic_error.html#invalid_operand) ⚠ Conditional expression should be 1-bit value ╭─[/home/hatta/work/repos/veryl/testcases/veryl/12_always.veryl:26:12] 25 │ always_ff { 26 │ if 1 { ·...

> I always thought that was a bit weird in SV. Shouldn't integer literals (and constant expressions of them) be arbitrary precision until they are used in a context that...

This PR should be merged after https://github.com/google/mdbook-i18n-helpers/pull/284 and new mdbook-i18n-helpers release.

For example, `` is already used as packed array notation, it may be suitable to bit concatenation. ```systemverilog let a: logic = ; assign = 1; always_comb { = 1;...

> Variadic functions are currently not possible, eh? If so, we could introduce a `concat` function. I think funciton style is suitable for right hand side, but not for left...

One more idea: using `,` as concatenation operator. This is consistent with multiple assignment in general programming languages. ```systemverilog let a: logic = x, y; assign x, y = 1;...