Naoya Hatta
Naoya Hatta
#908 seems to be related too.
I think interface inheritance / composition is better than code block approach in this case because code block provide only a feature like text macro and not special support for...
Sorry, I've mistakely closed.
Surely, it seems to be necessary. But I think the `inst` keyword is not proper, because the new syntax is bit differ than the existing `inst` declaration. (and it is...
Multiple inheritance and diamond problem should be considerd. ```systemverilog interface Base #( param WIDTH: u32 = 0, ) { var x: logic, } interface Req #( param WIDTH: u32 =...
Generally, there are several ways to resolve diamond problem. * Single inheritance only * Forbid nested inheritance * Check conflict at compile * Separated namespace for each inheritance path Even...
At the point of view of syntax complexity, adding `#[cond_type]` attribute instead of adding keywords may be better. ```systemverilog #[cond_type(unique)] case a { } #[cond_type(priority)] case a { } #[cond_type(unique0)]...
> I do not see how Veryl can possibly be expected to check condition overlapping. Yes. Veryl can't check overlapping in all cases. So at the most safe side, there...
I understood like below. Is this right? * When condition is static and overlapping check can be done by tools, synthesizer can optimize enough without these keywords. * When these...
I agree wrong usage of these keywords emits warning, but in many cases simulator works fine with warning messages. (Of course, we can configure to promote some warnings to hard...