Naoya Hatta

> We have to trust designer if RTL code including case/if statements with these quialifiers works correctly. > Therefore, I think Veryl should report information message when quialifiers are used....

I'm trying to implement this feature. The current spec is below: * Add attributes: * `#[cond_type(unique)]` * `#[cond_type(unique0)]` * `#[cond_type(priority)]` * `#[cond_type(none)]` `none` is used to control nested case like...

I found the same issue. My repository is https://github.com/veryl-lang/veryl . In this repo, I want to add `testcases/veryl` directory to watch list. So I wrote like below at first, but...

I think some way to realize it. * Add command line option to `veryl build` * Add project config to `Veryl.toml` * This config affects to the current project only...

I think there are two candidates. * Veryl compiler detects whteher each `case` statement need `inside`, and suppresses unnecessary `inside`. * User specify that each `case` statement require `inside` or...

I agree that this use case is common in FPGA. But I think allowing this feature unconditionally is not good. This is because ASIC synthesizers (possibly few FPGA synthesizer too?)...

By following code, clock polarity and reset type which Verilog module receives can be specified. Veryl compiler inserts `~` if polarity inversion is required at casting. ```systemverilog module Module (...

I think the following design may be acceptable. * Introduce `#[allow(initial_assign)]` ```systemverilog pub module RegisterFile ( i_clk: input clock, ) { var regs: logic[8]; #[allow(initial_assign)] initial { regs[0] = '0;...

I imagine FPGA users want to use `readmemh` to initialize ROM. So keeping to separate `initial` and `if_reset` may be better.

I think embedding the contents to SV is not good. This is because "fw.hex" can be changed after Veryl compilation. It causes mismatch between ASIC and FPGA, and it is...