CyrIng

[AMD][VMR/RPL/GNR] Voltage Curve Optimizer

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For AMD Vermeer, Raphael and Granite Ridge is introduced the VCO formula as a build argument: ```sh make -j HWM_CHIPSET=AMD_VCO ``` Remarks: * without the `HWM_CHIPSET` argument, the _CoreFreq_ build...

[AMD][Intel] Non-binary DDR5

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# DDR5 Query * [What is “non-binary” memory?](https://www.kingston.com/en/blog/system-builder/24gbit-memory-faq) * To decode the 24GB or 48GB DIMM geometry, **can anyone dump some registers ?** # [AMD] Zen 4 or 5 *...

[Contributors wanted!] Intel DTT

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I would like to add the DTT state in _CoreFreq_ Technologies We have specs at Intel for [gen. 12](https://edc.intel.com/content/www/us/en/design/publications/12th-generation-core-processor-datasheet-volume-2-of-2/d4-f0-dynamic-tuning-technology-registers-registers/) and we just need to probe registers at the PCI device...

Possible regression in the CCD cluster ID computation has been introduced by commit 6b28cc20071b7f4099fec6f186e133a8b5309be6 This impact per cluster sensor values like temperature, perhaps voltage Feel free to contact me whereas...