CoreFreq
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[Intel: Gen 12,13,14] Memory Controller data
Decoder has reporting issues among DDR4 and DDR5, two or four DIMMs, 32 or 64 bits per channel
Based on latest version 1.97.2; Owners of Intel Processors of 12th, 13th, 14th and above, please post the output of:
corefreq-cli -s -n -m -n -M -n -k -n -B
@BugReporterZ: #486 12th Gen Intel(R) Core(TM) i7-12700K
Processor [12th Gen Intel(R) Core(TM) i7-12700K]
|- Architecture [Alder Lake]
|- Vendor ID [GenuineIntel]
|- Microcode [0x00000035]
|- Signature [ 06_97]
|- Stepping [ 2]
|- Online CPU [ 20/ 20]
|- Base Clock [100.265]
|- Frequency (MHz) Ratio
Min 802.12 < 8 >
Max 3609.53 < 36 >
|- Factory [100.000]
3600 [ 36 ]
|- Performance
|- P-State
TGT 1102.91 < 11 >
|- HWP
Min 802.13 < 8 >
Max 6717.74 < 67 >
TGT AUTO < 0 >
|- Turbo Boost [ UNLOCK]
1C 5213.77 < 52 >
2C 5213.77 < 52 >
3C 5213.77 < 52 >
4C 5213.77 < 52 >
5C 5213.77 < 52 >
6C 5213.77 < 52 >
7C 5213.77 < 52 >
8C 5213.77 < 52 >
|- Hybrid [ UNLOCK]
1C 4010.63 < 40 >
2C 4010.63 < 40 >
3C 4010.63 < 40 >
4C 4010.63 < 40 >
5C 4010.63 < 40 >
6C 4010.63 < 40 >
7C 4010.63 < 40 >
8C 4010.63 < 40 >
|- Uncore [ UNLOCK]
Min 802.13 < 8 >
Max 4612.23 < 46 >
|- TDP Level [ 0:3 ]
|- Programmable [ UNLOCK]
|- Configuration [ LOCK]
|- Turbo Activation [ UNLOCK]
Nominal 3609.53 [ 36 ]
Turbo AUTO < 0 >
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AMX-BF16 [N] AMX-TILE [N] AMX-INT8 [N] AMX-FP16 [N]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] AVX-VNNI-VEX [Y] AVX-VNN-INT8 [N] AVX-NE-CONV [N]
|- AVX-IFMA [N] CMPccXADD [N] MOVDIRI [Y] MOVDIR64B [Y]
|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- ENQCMD [N] GFNI [Y] OSPKE [Y] WAITPKG [Y]
|- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y]
|- SERIALIZE [Y] SYSCALL [Y] RDPID [Y] SGX [N]
|- VAES [Y] VPCLMULQDQ [Y] PREFETCH/W [Y] LZCNT [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable]
|- CPL Qualified Debug Store DS-CPL [Capable]
|- 64-Bit Debug Store DTES64 [Capable]
|- Fast Short REP CMPSB FSRC [Missing]
|- Fast Short REP MOVSB FSRM [Capable]
|- Fast Short REP STOSB FSRS [Capable]
|- Fast Zero-length REP MOVSB FZRM [Missing]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA [Capable]
|- Flexible Return and Event Delivery FRED [Missing]
|- Hardware Feedback Interface HFI [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Hyper-Threading Technology HTT [Capable]
|- History Reset HRESET [Capable]
|- Hybrid part processor HYBRID [Capable]
|- Instruction Based Sampling IBS [Missing]
|- Instruction INVPCID INVPCID [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- Linear Address Space Separation LASS [Missing]
|- Linear Address Masking LAM [Missing]
|- Load Kernel GS segment register LKGS [Missing]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Capable]
|- Platform Configuration PCONFIG [Capable]
|- Process Context Identifiers PCID [Capable]
|- Perfmon and Debug Capability PDCM [Capable]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Write Data to a Processor Trace Packet PTWRITE [Capable]
|- PREFETCHIT0/1 Instructions PREFETCHI [Missing]
|- Resource Director Technology/PQE RDT-A [Missing]
|- Resource Director Technology/PQM RDT-M [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Capable]
|- Self-Snoop SS [Capable]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Thread Director TD [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Capable]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Capable]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Capable]
|- Write Back & Do Not Invalidate Cache WBNOINVD [Missing]
|- Extended xAPIC Support x2APIC [ x2APIC]
|- Execution Disable Bit Support XD-Bit [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Capable]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [ Enable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- Writeback & invalidate the L1 data cache L1D-FLUSH [Capable]
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [ Enable]
|- Arch - Buffer Overwriting MD-CLEAR [Capable]
|- Arch - No Rogue Data Cache Load RDCL_NO [ Enable]
|- Arch - Enhanced IBRS IBRS_ALL [ Enable]
|- Arch - Return Stack Buffer Alternate RSBA [Capable]
|- Arch - No Speculative Store Bypass SSB_NO [Capable]
|- Arch - No Microarchitectural Data Sampling MDS_NO [ Enable]
|- Arch - No TSX Asynchronous Abort TAA_NO [ Enable]
|- Arch - No Page Size Change MCE PSCHANGE_MC_NO [ Enable]
|- Arch - STLB QoS STLB [ Enable]
|- Arch - Functional Safety Island FuSa [ Enable]
|- Arch - RSM in CPL0 only RSM [ Enable]
|- Arch - Split Locked Access Exception SPLA [ Enable]
|- Arch - Snoop Filter QoS Mask SNOOP_FILTER [ Enable]
|- Arch - No Fast Predictive Store Forwarding PSFD [Capable]
|- Arch - Data Operand Independent Timing Mode DOITM [Capable]
|- Arch - Not affected by SBDR or SSDP SBDR_SSDP_NO [ Enable]
|- Arch - No Fill Buffer Stale Data Propagator FBSDP_NO [ Enable]
|- Arch - No Primary Stale Data Propagator PSDP_NO [ Enable]
|- Arch - Overwrite Fill Buffer values FB_CLEAR [Capable]
|- Arch - Special Register Buffer Data Sampling SRBDS [ Unable]
|- RDRAND and RDSEED mitigation RNGDS [ Unable]
|- Restricted Transactional Memory RTM [ Unable]
|- Verify Segment for Writing instruction VERW [ Unable]
|- Arch - Restricted RSB Alternate RRSBA [ Enable]
|- Arch - No Branch Target Injection BHI_NO [Capable]
|- Arch - Legacy xAPIC Disable XAPIC_DIS [ Unable]
|- Arch - No Post-Barrier Return Stack Buffer PBRSB_NO [Capable]
|- Arch - IPRED disabled for CPL3 IPRED_DIS_U [Capable]
|- Arch - IPRED disabled for CPL0/1/2 IPRED_DIS_S [Capable]
|- Arch - RRSBA disabled for CPL3 RRSBA_DIS_U [Capable]
|- Arch - RRSBA disabled for CPL0/1/2 RRSBA_DIS_S [Capable]
|- Arch - Data Dependent Prefetcher CPL3 DDPD_U_DIS [ Unable]
|- Arch - BHI disabled for CPL0/1/2 BHI_DIS_S [ Enable]
|- No MXCSR Configuration Dependent Timing MCDT_NO [ Unable]
|- Overclocking
|- Overclocking Utilized UTILIZED [ Enable]
|- Undervolt Protection UVP [ Enable]
|- Overclocking Secure Status UNLOCKED [Capable]
Security Features
|- CPUID Key Locker KL [Capable]
|- AES Key Locker instructions AESKLE [Missing]
|- CET Shadow Stack features CET-SS [Capable]
|- CET Indirect Branch Tracking CET-IBT [Capable]
|- CET Supervisor Shadow Stack CET-SSS [Capable]
|- AES Wide Key Locker instructions WIDE_KL [Capable]
|- Software Guard SGX1 Extensions SGX1 [Missing]
|- Software Guard SGX2 Extensions SGX2 [Missing]
Technologies
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- L1 IP Prefetcher L1 HW IP < ON>
|- L1 Next Page Prefetcher L1 NPP <OFF>
|- L1 Scrubbing L1 Scrubbing <OFF>
|- Cache Prefetchers
|- L2 Prefetcher L2 HW < ON>
|- L2 Adjacent Cache Line Prefetcher L2 HW CL < ON>
|- L2 Adaptive Multipath Probability L2 AMP <OFF>
|- L2 Next Line Prefetcher L2 NLP <OFF>
|- LLC Streamer LLC < ON>
|- System Management Mode SMM-Dual [ ON]
|- Hyper-Threading HTT [ ON]
|- SpeedStep EIST < ON>
|- Dynamic Acceleration IDA [ ON]
|- Turbo Boost Max 3.0 TURBO < ON>
|- Energy Efficiency Optimization EEO <OFF>
|- Race To Halt Optimization R2H <OFF>
|- Watchdog Timer TCO <OFF>
|- Virtualization VMX [ ON]
|- I/O MMU VT-d [ ON]
|- Version [ 4.0]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [ 5]
|- Counters: General Fixed
| { 6, 0, 0 } x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E < ON>
|- C1 Auto Demotion C1A < ON>
|- C3 Auto Demotion C3A <OFF>
|- C1 UnDemotion C1U < ON>
|- C3 UnDemotion C3U <OFF>
|- C6 Core Demotion CC6 <OFF>
|- C6 Module Demotion MC6 <OFF>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-States
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT < C0>
|- I/O MWAIT Redirection IOMWAIT <Disable>
|- Max C-State Inclusion RANGE < C8>
|- Core C-States
|- C-States Base Address BAR [ 0x1814]
|- ACPI Processor C-States _CST [ 3]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 0 2 0 2 0 1 0 1
|- Monitor-Mwait Extensions EMX [Capable]
|- Interrupt Break-Event IBE [Capable]
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Last Level Cache Misses [Capable]
|- Branch Instructions Retired [Capable]
|- Branch Mispredicts Retired [Capable]
|- Top-down slots Counter [Capable]
|- Processor Performance Control _PCT [ Enable]
|- Performance Supported States _PSS [ 0]
|- Performance Present Capabilities _PPC [ 0]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax < 0: 82 C>
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ UNLOCK]
|- Energy Policy Bias Hint < 6>
|- Energy Policy HWP EPP < 128>
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Capable]
|- Package Thermal Management PTM [Capable]
|- Thermal Monitor 1 TM1 [ Enable]
|- Thermal Monitor 2 TM2 [Capable]
|- Thermal Design Power TDP [ 125 W]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package < Enable>
|- Power Limit PL1 < 125 W>
|- Time Window TW1 < 2m08s>
|- Power Limit PL2 < 190 W>
|- Time Window TW2 < 2 ms>
|- Thermal Design Power Core <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power Uncore <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power DRAM <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power Platform <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 28 s>
|- Power Limit PL2 < 0 W>
|- Time Window TW2 < 976 us>
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Package Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000061035]
|- Window second [ 0.000976562]
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID Hybrid ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 P 1 0 0 32768 8 49152 12 1310720 10 26214400 10
001: 0 1 P 1 0 1 32768 8 49152 12 1310720 10 26214400 10
002: 0 8 P 1 4 0 32768 8 49152 12 1310720 10 26214400 10
003: 0 9 P 1 4 1 32768 8 49152 12 1310720 10 26214400 10
004: 0 16 P 1 8 0 32768 8 49152 12 1310720 10 26214400 10
005: 0 17 P 1 8 1 32768 8 49152 12 1310720 10 26214400 10
006: 0 24 P 1 12 0 32768 8 49152 12 1310720 10 26214400 10
007: 0 25 P 1 12 1 32768 8 49152 12 1310720 10 26214400 10
008: 0 32 P 1 16 0 32768 8 49152 12 1310720 10 26214400 10
009: 0 33 P 1 16 1 32768 8 49152 12 1310720 10 26214400 10
010: 0 40 P 1 20 0 32768 8 49152 12 1310720 10 26214400 10
011: 0 41 P 1 20 1 32768 8 49152 12 1310720 10 26214400 10
012: 0 48 P 1 24 0 32768 8 49152 12 1310720 10 26214400 10
013: 0 49 P 1 24 1 32768 8 49152 12 1310720 10 26214400 10
014: 0 56 P 1 28 0 32768 8 49152 12 1310720 10 26214400 10
015: 0 57 P 1 28 1 32768 8 49152 12 1310720 10 26214400 10
016: 0 72 E 1 36 0 65536 8 32768 8 2097152 16 26214400 10
017: 0 74 E 1 37 0 65536 8 32768 8 2097152 16 26214400 10
018: 0 76 E 1 38 0 65536 8 32768 8 2097152 16 26214400 10
019: 0 78 E 1 39 0 65536 8 32768 8 2097152 16 26214400 10
Intel Z690 [7A84]
Controller #0 Dual Channel
Bus Rate 3600 MHz Bus Speed 3609 MHz DDR4 Speed 7218 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 18 22 22 22 42 4 9 40 24 12 46 18 7 2T
#1 5 8 8 8 28 4 4 16 14 6 24 6 4 1T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 7 4 12 12 14 15 15 16 36 29 7 7
#1 4 4 4 4 4 4 4 4 4 4 4 4
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 7 4 12 12 14055 630 648 11 4 1 0
#1 4 4 4 4 4100 180 0 4 1 1 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 65536 1024 16384 CMK32GX4M2D3600C18
#1 16 2 65536 1024 16384 CMK32GX4M2D3600C18
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
Controller #1 Dual Channel
Bus Rate 3600 MHz Bus Speed 3609 MHz DDR4 Speed 7218 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 18 22 22 22 42 4 9 40 24 12 46 18 7 2T
#1 5 8 8 8 28 4 4 16 14 6 24 6 4 1T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 7 4 12 12 14 15 15 16 36 29 7 7
#1 4 4 4 4 4 4 4 4 4 4 4 4
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 7 4 12 12 14055 630 648 11 4 1 0
#1 4 4 4 4 4100 180 0 4 1 1 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 65536 1024 16384 CMK32GX4M2D3600C18
#1 16 2 65536 1024 16384 CMK32GX4M2D3600C18
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
Linux:
|- Release [6.8.9-1-default]
|- Version [#1 SMP PREEMPT_DYNAMIC Fri May 10 08:51:14 UTC 2024 (d3445e0)]
|- Machine [x86_64]
Memory:
|- Total RAM 65530632 KB
|- Shared RAM 1313640 KB
|- Free RAM 49791360 KB
|- Buffer RAM 2712 KB
|- Total High 0 KB
|- Free High 0 KB
Clock Source < tsc>
CPU-Freq driver [ intel_pstate]
Governor [ Missing]
CPU-Idle driver [ intel_idle]
|- Idle Limit [ C10]
|- State POLL C1E C6 C8 C10
|- CPUIDLE MWAIT 0 MWAIT 0 MWAIT 0 MWAIT 0
|- Power -1 0 0 0 0
|- Latency 0 2 220 280 680
|- Residency 0 4 600 800 2000
[ 0] American Megatrends International, LLC.
[ 1] 1.H0
[ 2] 03/29/2024
[ 3] Micro-Star International Co., Ltd.
[ 4] MS-7D25
[ 5] 1.0
[ 6] D---u---s---n-
[ 7] Default string
[ 8] Default string
[ 9] Micro-Star International Co., Ltd.
[10] PRO Z690-A WIFI DDR4(MS-7D25)
[11] 1.0
[12] 0---5---L---0---8-
[13] Number Of Devices:4\Maximum Capacity:134217728 kilobytes
[14] Controller0-DIMMA1\BANK 0
[15] Controller0-DIMMA2\BANK 0
[16] Controller1-DIMMB1\BANK 0
[17] Controller1-DIMMB2\BANK 0
[18] Corsair
[19] Corsair
[20] Corsair
[21] Corsair
[22] CMK32GX4M2D3600C18
[23] CMK32GX4M2D3600C18
[24] CMK32GX4M2D3600C18
[25] CMK32GX4M2D3600C18
In branch develop, commit c376448200f46da0444be3f26d93351a13367137 brings a decoder of the Meteor Lake memory controller
Decoder has been programmed from the Core Ultra Processor datasheets
I will appreciate if anyone could show me the result, either corefreq-cli -M or UI screenshot
Not sure if that was meant for Meteor Lake users, but on my own I get this:
./build/corefreq-cli -M
Intel Z690 [7A84]
Controller #0 Dual Channel
Bus Rate 3600 MHz Bus Speed 3609 MHz DDR4 Speed 7219 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 18 22 22 22 42 4 9 40 24 12 46 18 7 2T
#1 5 8 8 8 28 4 4 16 14 6 24 6 4 1T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 7 4 12 12 14 15 15 16 36 29 7 7
#1 4 4 4 4 4 4 4 4 4 4 4 4
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 7 4 12 12 14055 630 648 11 4 1 0
#1 4 4 4 4 4100 180 0 4 1 1 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 65536 1024 16384 CMK32GX4M2D3600C18
#1 16 2 65536 1024 16384 CMK32GX4M2D3600C18
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
Controller #1 Dual Channel
Bus Rate 3600 MHz Bus Speed 3609 MHz DDR4 Speed 7219 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 18 22 22 22 42 4 9 40 24 12 46 18 7 2T
#1 5 8 8 8 28 4 4 16 14 6 24 6 4 1T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 7 4 12 12 14 15 15 16 36 29 7 7
#1 4 4 4 4 4 4 4 4 4 4 4 4
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 7 4 12 12 14055 630 648 11 4 1 0
#1 4 4 4 4 4100 180 0 4 1 1 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 65536 1024 16384 CMK32GX4M2D3600C18
#1 16 2 65536 1024 16384 CMK32GX4M2D3600C18
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
@BugReporterZ thanks; it was indeed meant for Meteor Lake
I also want to debug previous generations IMC; your output helps a lot but I need other combinations of DDR4, DDR5, 32 or 64 bits DIMM, LP-DDR and so on to solve my decoders.
Source: Intel
From MADCH.DDR_TYPE we can tell if LPDDR5 or DDR5 is set up with ADL and compatible but also MTL
Still no clue from register MAD_DIMM how to decode the new DIMM kind of 24 or 48 GB size with ADL or MTL
root@pve:~# corefreq-cli -s -n -m -n -M -n -k -n -B
Processor [Intel(R) Core(TM) i7-14700K]
|- Architecture [Raptor Lake]
|- Vendor ID [GenuineIntel]
|- Microcode [0x0000011d]
|- Signature [ 06_B7]
|- Stepping [ 1]
|- Online CPU [ 20/ 20]
|- Base Clock [100.515]
|- Frequency (MHz) Ratio
Min 804.12 < 8 >
Max 3417.52 < 34 >
|- Factory [100.000]
3400 [ 34 ]
|- Performance
TGT 7036.07 < 70 >
|- HWP
Min 4322.21 < 43 >
Max 7036.07 < 70 >
TGT AUTO < 0 >
|- Turbo Boost [ UNLOCK]
1C 5628.85 < 56 >
2C 5628.85 < 56 >
3C 5528.34 < 55 >
4C 5528.34 < 55 >
5C 5528.34 < 55 >
6C 5528.34 < 55 >
7C 5528.34 < 55 >
8C 5528.34 < 55 >
|- Hybrid [ UNLOCK]
1C 4322.17 < 43 >
|- Uncore [ UNLOCK]
Min 804.12 < 8 >
Max 5025.78 < 50 >
|- TDP Level [ 0:0 ]
|- Programmable [ UNLOCK]
|- Configuration [ LOCK]
|- Turbo Activation [ UNLOCK]
Nominal 3417.52 [ 34 ]
Turbo AUTO < 0 >
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AMX-BF16 [N] AMX-TILE [N] AMX-INT8 [N] AMX-FP16 [N]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] AVX-VNNI-VEX [Y] AVX-VNN-INT8 [N] AVX-NE-CONV [N]
|- AVX-IFMA [N] CMPccXADD [N] MOVDIRI [Y] MOVDIR64B [Y]
|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- ENQCMD [N] GFNI [Y] OSPKE [Y] WAITPKG [Y]
|- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y]
|- SERIALIZE [Y] SYSCALL [Y] RDPID [Y] SGX [N]
|- VAES [Y] VPCLMULQDQ [Y] PREFETCH/W [Y] LZCNT [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable]
|- CPL Qualified Debug Store DS-CPL [Capable]
|- 64-Bit Debug Store DTES64 [Capable]
|- Fast Short REP CMPSB FSRC [Missing]
|- Fast Short REP MOVSB FSRM [Capable]
|- Fast Short REP STOSB FSRS [Capable]
|- Fast Zero-length REP MOVSB FZRM [Missing]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA [Capable]
|- Flexible Return and Event Delivery FRED [Missing]
|- Hardware Feedback Interface HFI [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Hyper-Threading Technology HTT [Capable]
|- History Reset HRESET [Capable]
|- Hybrid part processor HYBRID [Capable]
|- Instruction Based Sampling IBS [Missing]
|- Instruction INVPCID INVPCID [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- Linear Address Space Separation LASS [Missing]
|- Linear Address Masking LAM [Missing]
|- Load Kernel GS segment register LKGS [Missing]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Capable]
|- Platform Configuration PCONFIG [Capable]
|- Process Context Identifiers PCID [Capable]
|- Perfmon and Debug Capability PDCM [Capable]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Write Data to a Processor Trace Packet PTWRITE [Capable]
|- PREFETCHIT0/1 Instructions PREFETCHI [Missing]
|- Resource Director Technology/PQE RDT-A [Missing]
|- Resource Director Technology/PQM RDT-M [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Capable]
|- Self-Snoop SS [Capable]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Thread Director TD [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Capable]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Capable]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Capable]
|- Write Back & Do Not Invalidate Cache WBNOINVD [Missing]
|- Extended xAPIC Support x2APIC [ x2APIC]
|- Execution Disable Bit Support XD-Bit [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Capable]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [ Enable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- Writeback & invalidate the L1 data cache L1D-FLUSH [Capable]
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [ Enable]
|- Arch - Buffer Overwriting MD-CLEAR [Capable]
|- Arch - No Rogue Data Cache Load RDCL_NO [ Enable]
|- Arch - Enhanced IBRS IBRS_ALL [ Enable]
|- Arch - Return Stack Buffer Alternate RSBA [Capable]
|- Arch - No Speculative Store Bypass SSB_NO [Capable]
|- Arch - No Microarchitectural Data Sampling MDS_NO [Capable]
|- Arch - No TSX Asynchronous Abort TAA_NO [Capable]
|- Arch - No Page Size Change MCE PSCHANGE_MC_NO [Capable]
|- Arch - STLB QoS STLB [ Enable]
|- Arch - Functional Safety Island FuSa [ Enable]
|- Arch - RSM in CPL0 only RSM [ Enable]
|- Arch - Split Locked Access Exception SPLA [ Enable]
|- Arch - Snoop Filter QoS Mask SNOOP_FILTER [ Enable]
|- Arch - No Fast Predictive Store Forwarding PSFD [Capable]
|- Arch - Data Operand Independent Timing Mode DOITM [Capable]
|- Arch - Not affected by SBDR or SSDP SBDR_SSDP_NO [ Enable]
|- Arch - No Fill Buffer Stale Data Propagator FBSDP_NO [ Enable]
|- Arch - No Primary Stale Data Propagator PSDP_NO [ Enable]
|- Arch - Overwrite Fill Buffer values FB_CLEAR [Capable]
|- Arch - Special Register Buffer Data Sampling SRBDS [ Unable]
|- RDRAND and RDSEED mitigation RNGDS [ Unable]
|- Restricted Transactional Memory RTM [ Unable]
|- Verify Segment for Writing instruction VERW [ Unable]
|- Arch - Restricted RSB Alternate RRSBA [ Enable]
|- Arch - No Branch Target Injection BHI_NO [Capable]
|- Arch - Legacy xAPIC Disable XAPIC_DIS [ Unable]
|- Arch - No Post-Barrier Return Stack Buffer PBRSB_NO [Capable]
|- Arch - No Gather Data Sampling GDS_NO [ Enable]
|- Arch - No Register File Data Sampling RFDS_NO [Capable]
|- Arch - IPRED disabled for CPL3 IPRED_DIS_U [Capable]
|- Arch - IPRED disabled for CPL0/1/2 IPRED_DIS_S [Capable]
|- Arch - RRSBA disabled for CPL3 RRSBA_DIS_U [Capable]
|- Arch - RRSBA disabled for CPL0/1/2 RRSBA_DIS_S [Capable]
|- Arch - Data Dependent Prefetcher CPL3 DDPD_U_DIS [Capable]
|- Arch - BHI disabled for CPL0/1/2 BHI_DIS_S [ Enable]
|- No MXCSR Configuration Dependent Timing MCDT_NO [ Unable]
|- No MONITOR/UMONITOR mitigation UMON_MITG_NO [ Unable]
|- Overclocking
|- Overclocking Utilized UTILIZED [ Enable]
|- Undervolt Protection UVP [Capable]
|- Overclocking Secure Status UNLOCKED [Capable]
Security Features
|- CPUID Key Locker KL [Capable]
|- AES Key Locker instructions AESKLE [Missing]
|- CET Shadow Stack features CET-SS [Capable]
|- CET Indirect Branch Tracking CET-IBT [Capable]
|- CET Supervisor Shadow Stack CET-SSS [Capable]
|- AES Wide Key Locker instructions WIDE_KL [Capable]
|- Software Guard SGX1 Extensions SGX1 [Missing]
|- Software Guard SGX2 Extensions SGX2 [Missing]
Technologies
|- Data Cache Unit
|- L1 Prefetcher L1 HW <OFF>
|- L1 IP Prefetcher L1 HW IP < ON>
|- L1 Next Page Prefetcher L1 NPP <OFF>
|- L1 Scrubbing L1 Scrubbing <OFF>
|- Cache Prefetchers
|- L2 Prefetcher L2 HW < ON>
|- L2 Adjacent Cache Line Prefetcher L2 HW CL < ON>
|- L2 Adaptive Multipath Probability L2 AMP <OFF>
|- L2 Next Line Prefetcher L2 NLP <OFF>
|- LLC Streamer LLC < ON>
|- System Management Mode SMM-Dual [ ON]
|- Hyper-Threading HTT [OFF]
|- SpeedStep EIST < ON>
|- Dynamic Acceleration IDA [ ON]
|- Turbo Boost Max 3.0 TURBO < ON>
|- Energy Efficiency Optimization EEO <OFF>
|- Race To Halt Optimization R2H <OFF>
|- Watchdog Timer TCO <OFF>
|- Virtualization VMX [ ON]
|- I/O MMU VT-d [OFF]
|- Version [ N/A]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
|- Volume Management Device VMD [OFF]
|- Gaussian & Neural Accelerator GNA [OFF]
|- Digital Content Protection HDCP [OFF]
|- Image Processing Unit IPU [OFF]
|- Vision Processing Unit VPU [OFF]
|- Overclocking OC [OFF]
Performance Monitoring
|- Version PM [ 5]
|- Counters: General Fixed
| { 6, 0, 0 } x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E <OFF>
|- C1 Auto Demotion C1A < ON>
|- C3 Auto Demotion C3A <OFF>
|- C1 UnDemotion C1U < ON>
|- C3 UnDemotion C3U <OFF>
|- C6 Core Demotion CC6 <OFF>
|- C6 Module Demotion MC6 <OFF>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-States
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT < C0>
|- I/O MWAIT Redirection IOMWAIT <Disable>
|- Max C-State Inclusion RANGE < C1>
|- Core C-States
|- C-States Base Address BAR [ 0x1814]
|- ACPI Processor C-States _CST [ 2]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 0 2 0 2 0 1 0 1
|- Monitor-Mwait Extensions EMX [Capable]
|- Interrupt Break-Event IBE [Capable]
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Last Level Cache Misses [Capable]
|- Branch Instructions Retired [Capable]
|- Branch Mispredicts Retired [Capable]
|- Top-down slots Counter [Capable]
|- Processor Performance Control _PCT [ Enable]
|- Performance Supported States _PSS [ 0]
|- Performance Present Capabilities _PPC [ 0]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax < 0:100 C>
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint [ 0]
|- Energy Policy HWP EPP < 0>
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Capable]
|- Package Thermal Management PTM [Capable]
|- Thermal Monitor 1 TM1 [ Enable]
|- Thermal Monitor 2 TM2 [Capable]
|- Thermal Design Power TDP [ 125 W]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package < Enable>
|- Power Limit PL1 < 4095 W>
|- Time Window TW1 < 56 s>
|- Power Limit PL2 < 4095 W>
|- Time Window TW2 < 2 ms>
|- Thermal Design Power Core <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power Uncore <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power DRAM [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 976 us]
|- Thermal Design Power Platform <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 28 s>
|- Power Limit PL2 < 0 W>
|- Time Window TW2 < 976 us>
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Package Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000061035]
|- Window second [ 0.000976562]
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID Hybrid ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 P 1 0 0 32768 8 49152 12 2097152 16 34603008 11
001: 0 8 P 1 4 0 32768 8 49152 12 2097152 16 34603008 11
002: 0 16 P 1 8 0 32768 8 49152 12 2097152 16 34603008 11
003: 0 24 P 1 12 0 32768 8 49152 12 2097152 16 34603008 11
004: 0 32 P 1 16 0 32768 8 49152 12 2097152 16 34603008 11
005: 0 40 P 1 20 0 32768 8 49152 12 2097152 16 34603008 11
006: 0 48 P 1 24 0 32768 8 49152 12 2097152 16 34603008 11
007: 0 56 P 1 28 0 32768 8 49152 12 2097152 16 34603008 11
008: 0 64 E 1 32 0 65536 8 32768 8 4194304 16 34603008 11
009: 0 66 E 1 33 0 65536 8 32768 8 4194304 16 34603008 11
010: 0 68 E 1 34 0 65536 8 32768 8 4194304 16 34603008 11
011: 0 70 E 1 35 0 65536 8 32768 8 4194304 16 34603008 11
012: 0 72 E 1 36 0 65536 8 32768 8 4194304 16 34603008 11
013: 0 74 E 1 37 0 65536 8 32768 8 4194304 16 34603008 11
014: 0 76 E 1 38 0 65536 8 32768 8 4194304 16 34603008 11
015: 0 78 E 1 39 0 65536 8 32768 8 4194304 16 34603008 11
016: 0 80 E 1 40 0 65536 8 32768 8 4194304 16 34603008 11
017: 0 82 E 1 41 0 65536 8 32768 8 4194304 16 34603008 11
018: 0 84 E 1 42 0 65536 8 32768 8 4194304 16 34603008 11
019: 0 86 E 1 43 0 65536 8 32768 8 4194304 16 34603008 11
Intel Z790 [7A04]
Linux:
|- Release [6.8.8-3-pve]
|- Version [#1 SMP PREEMPT_DYNAMIC PMX 6.8.8-3 (2024-07-16T16:16Z)]
|- Machine [x86_64]
Memory:
|- Total RAM 65604240 KB
|- Shared RAM 59220 KB
|- Free RAM 63263024 KB
|- Buffer RAM 84928 KB
|- Total High 0 KB
|- Free High 0 KB
Clock Source < tsc>
CPU-Freq driver [ intel_pstate]
Governor [ Missing]
CPU-Idle driver [ intel_idle]
|- Idle Limit [ C2_ACPI]
|- State POLL C1_ACPI C2_ACPI
|- CPUIDLE ACPI FF ACPI FF
|- Power -1 0 0
|- Latency 0 1 127
|- Residency 0 1 381
[ 0] American Megatrends International, LLC.
[ 1] M.00
[ 2] 09/06/2023
[ 3] Micro-Star International Co., Ltd.
[ 4] MS-7E07
[ 5] 4.0
[ 6] D---u---s---n-
[ 7] Default string
[ 8] Default string
[ 9] Micro-Star International Co., Ltd.
[10] PRO Z790-A MAX WIFI (MS-7E07)
[11] 4.0
[12] 0---7---N---4---5-
[13] Number Of Devices:4\Maximum Capacity:134217728 kilobytes
[14]
[15] Controller0-DIMMA2\BANK 0
[16]
[17] Controller1-DIMMB2\BANK 0
[18]
[19] 0x0B92
[20]
[21] 0x0B92
[22]
[23]
[24]
[25]
@paulzzh Thank you for your Raptor output I don't have its Memory Controller device identifier. Can you please post the output of the following command:
lspci -nn
@paulzzh Thank you for your Raptor output I don't have its Memory Controller device identifier. Can you please post the output of the following command:
lspci -nn
root@pve:~# lspci -nn
00:00.0 Host bridge [0600]: Intel Corporation Device [8086:a740] (rev 01)
00:02.0 VGA compatible controller [0300]: Intel Corporation Raptor Lake-S GT1 [UHD Graphics 770] [8086:a780] (rev 04)
00:02.1 VGA compatible controller [0300]: Intel Corporation Raptor Lake-S GT1 [UHD Graphics 770] [8086:a780] (rev 04)
00:02.2 VGA compatible controller [0300]: Intel Corporation Raptor Lake-S GT1 [UHD Graphics 770] [8086:a780] (rev 04)
00:02.3 VGA compatible controller [0300]: Intel Corporation Raptor Lake-S GT1 [UHD Graphics 770] [8086:a780] (rev 04)
00:02.4 VGA compatible controller [0300]: Intel Corporation Raptor Lake-S GT1 [UHD Graphics 770] [8086:a780] (rev 04)
00:02.5 VGA compatible controller [0300]: Intel Corporation Raptor Lake-S GT1 [UHD Graphics 770] [8086:a780] (rev 04)
00:02.6 VGA compatible controller [0300]: Intel Corporation Raptor Lake-S GT1 [UHD Graphics 770] [8086:a780] (rev 04)
00:02.7 VGA compatible controller [0300]: Intel Corporation Raptor Lake-S GT1 [UHD Graphics 770] [8086:a780] (rev 04)
00:06.0 PCI bridge [0604]: Intel Corporation Raptor Lake PCIe 4.0 Graphics Port [8086:a74d] (rev 01)
00:08.0 System peripheral [0880]: Intel Corporation GNA Scoring Accelerator module [8086:a74f] (rev 01)
00:0a.0 Signal processing controller [1180]: Intel Corporation Raptor Lake Crashlog and Telemetry [8086:a77d] (rev 01)
00:14.0 USB controller [0c03]: Intel Corporation Raptor Lake USB 3.2 Gen 2x2 (20 Gb/s) XHCI Host Controller [8086:7a60] (rev 11)
00:14.2 RAM memory [0500]: Intel Corporation Raptor Lake-S PCH Shared SRAM [8086:7a27] (rev 11)
00:16.0 Communication controller [0780]: Intel Corporation Raptor Lake CSME HECI [8086:7a68] (rev 11)
00:17.0 SATA controller [0106]: Intel Corporation Raptor Lake SATA AHCI Controller [8086:7a62] (rev 11)
00:1c.0 PCI bridge [0604]: Intel Corporation Raptor Lake PCI Express Root Port [8086:7a38] (rev 11)
00:1c.2 PCI bridge [0604]: Intel Corporation Device [8086:7a3a] (rev 11)
00:1c.3 PCI bridge [0604]: Intel Corporation Raptor Lake PCI Express Root Port [8086:7a3b] (rev 11)
00:1d.0 PCI bridge [0604]: Intel Corporation Raptor Lake PCI Express Root Port [8086:7a30] (rev 11)
00:1f.0 ISA bridge [0601]: Intel Corporation Raptor Lake LPC/eSPI Controller [8086:7a04] (rev 11)
00:1f.3 Audio device [0403]: Intel Corporation Raptor Lake High Definition Audio Controller [8086:7a50] (rev 11)
00:1f.4 SMBus [0c05]: Intel Corporation Raptor Lake-S PCH SMBus Controller [8086:7a23] (rev 11)
00:1f.5 Serial bus controller [0c80]: Intel Corporation Raptor Lake SPI (flash) Controller [8086:7a24] (rev 11)
01:00.0 Non-Volatile memory controller [0108]: Intel Corporation NVMe Optane Memory Series [8086:2522]
03:00.0 Network controller [0280]: Qualcomm Technologies, Inc WCN785x Wi-Fi 7(802.11be) 320MHz 2x2 [FastConnect 7800] [17cb:1107] (rev 01)
04:00.0 Ethernet controller [0200]: Intel Corporation Ethernet Controller I225-V [8086:15f3] (rev 03)
05:00.0 Non-Volatile memory controller [0108]: MAXIO Technology (Hangzhou) Ltd. NVMe SSD Controller MAP1602 (DRAM-less) [1e4b:1602] (rev 01)
@paulzzh
Your Host bridge [8086:a740] has been added to probe the Memory Controller
You can now pull the develop branch; rebuild and reload CoreFreq (especially its driver corefreqk.ko)
Can you then post the output of corefreq-cli -s -n -M and tell how results match with your setup ?
@paulzzh
Your
Host bridge [8086:a740]has been added to probe the Memory Controller You can now pull thedevelopbranch; rebuild and reload CoreFreq (especially its drivercorefreqk.ko) Can you then post the output ofcorefreq-cli -s -n -Mand tell how results match with your setup ?
It seems to work.
root@pve:~# corefreq-cli -s -n -M
Processor [Intel(R) Core(TM) i7-14700K]
|- Architecture [Raptor Lake]
|- Vendor ID [GenuineIntel]
|- Microcode [0x00000123]
|- Signature [ 06_B7]
|- Stepping [ 1]
|- Online CPU [ 20/ 20]
|- Base Clock [100.509]
|- Frequency (MHz) Ratio
Min 804.07 < 8 >
Max 3417.30 < 34 >
|- Factory [100.000]
3400 [ 34 ]
|- Performance
TGT 7236.64 < 72 >
|- HWP
Min 4321.92 < 43 >
Max 7236.64 < 72 >
TGT AUTO < 0 >
|- Turbo Boost [ UNLOCK]
1C 5628.49 < 56 >
2C 5628.49 < 56 >
3C 5527.99 < 55 >
4C 5527.99 < 55 >
5C 5527.99 < 55 >
6C 5527.99 < 55 >
7C 5527.99 < 55 >
8C 5527.99 < 55 >
|- Hybrid [ UNLOCK]
1C 4321.97 < 43 >
|- Uncore [ UNLOCK]
Min 804.09 < 8 >
Max 5025.55 < 50 >
|- TDP Level [ 0:3 ]
|- Programmable [ UNLOCK]
|- Configuration [ LOCK]
|- Turbo Activation [ UNLOCK]
Nominal 3417.30 [ 34 ]
Turbo AUTO < 0 >
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AMX-BF16 [N] AMX-TILE [N] AMX-INT8 [N] AMX-FP16 [N]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] AVX-VNNI-VEX [Y] AVX-VNN-INT8 [N] AVX-NE-CONV [N]
|- AVX-IFMA [N] CMPccXADD [N] MOVDIRI [Y] MOVDIR64B [Y]
|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- ENQCMD [N] GFNI [Y] OSPKE [Y] WAITPKG [Y]
|- MMX/Ext [Y/N] MON/MWAITX [Y/N] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/N] SSE4.2 [Y]
|- SERIALIZE [Y] SYSCALL [Y] RDPID [Y] SGX [N]
|- VAES [Y] VPCLMULQDQ [Y] PREFETCH/W [Y] LZCNT [Y]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- Core Multi-Processing CMP Legacy [Missing]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Capable]
|- CPL Qualified Debug Store DS-CPL [Capable]
|- 64-Bit Debug Store DTES64 [Capable]
|- Fast Short REP CMPSB FSRC [Missing]
|- Fast Short REP MOVSB FSRM [Capable]
|- Fast Short REP STOSB FSRS [Capable]
|- Fast Zero-length REP MOVSB FZRM [Missing]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA [Capable]
|- Flexible Return and Event Delivery FRED [Missing]
|- Hardware Feedback Interface HFI [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Hyper-Threading Technology HTT [Capable]
|- History Reset HRESET [Capable]
|- Hybrid part processor HYBRID [Capable]
|- Instruction Based Sampling IBS [Missing]
|- Instruction INVPCID INVPCID [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- Linear Address Space Separation LASS [Missing]
|- Linear Address Masking LAM [Missing]
|- Load Kernel GS segment register LKGS [Missing]
|- LightWeight Profiling LWP [Missing]
|- Machine-Check Architecture MCA [Capable]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Capable]
|- Platform Configuration PCONFIG [Capable]
|- Process Context Identifiers PCID [Capable]
|- Perfmon and Debug Capability PDCM [Capable]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Write Data to a Processor Trace Packet PTWRITE [Capable]
|- PREFETCHIT0/1 Instructions PREFETCHI [Missing]
|- Resource Director Technology/PQE RDT-A [Missing]
|- Resource Director Technology/PQM RDT-M [Missing]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Capable]
|- Self-Snoop SS [Capable]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Thread Director TD [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Capable]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Capable]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Capable]
|- Write Back & Do Not Invalidate Cache WBNOINVD [Missing]
|- Extended xAPIC Support x2APIC [ x2APIC]
|- Execution Disable Bit Support XD-Bit [Capable]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Capable]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Capable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [Capable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- Writeback & invalidate the L1 data cache L1D-FLUSH [Capable]
|- Hypervisor - No flush L1D on VM entry L1DFL_VMENTRY_NO [Capable]
|- Arch - Buffer Overwriting MD-CLEAR [Capable]
|- Arch - No Rogue Data Cache Load RDCL_NO [Capable]
|- Arch - Enhanced IBRS IBRS_ALL [Capable]
|- Arch - Return Stack Buffer Alternate RSBA [Capable]
|- Arch - No Speculative Store Bypass SSB_NO [Capable]
|- Arch - No Microarchitectural Data Sampling MDS_NO [Capable]
|- Arch - No TSX Asynchronous Abort TAA_NO [Capable]
|- Arch - No Page Size Change MCE PSCHANGE_MC_NO [Capable]
|- Arch - STLB QoS STLB [ Enable]
|- Arch - Functional Safety Island FuSa [ Enable]
|- Arch - RSM in CPL0 only RSM [ Enable]
|- Arch - Split Locked Access Exception SPLA [ Enable]
|- Arch - Snoop Filter QoS Mask SNOOP_FILTER [ Enable]
|- Arch - No Fast Predictive Store Forwarding PSFD [Capable]
|- Arch - Data Operand Independent Timing Mode DOITM [ Unable]
|- Arch - Not affected by SBDR or SSDP SBDR_SSDP_NO [Capable]
|- Arch - No Fill Buffer Stale Data Propagator FBSDP_NO [Capable]
|- Arch - No Primary Stale Data Propagator PSDP_NO [Capable]
|- Arch - Overwrite Fill Buffer values FB_CLEAR [Capable]
|- Arch - Special Register Buffer Data Sampling SRBDS [ Unable]
|- RDRAND and RDSEED mitigation RNGDS [ Unable]
|- Restricted Transactional Memory RTM [ Unable]
|- Verify Segment for Writing instruction VERW [ Unable]
|- Arch - Restricted RSB Alternate RRSBA [Capable]
|- Arch - No Branch Target Injection BHI_NO [Capable]
|- Arch - Legacy xAPIC Disable XAPIC_DIS [ Unable]
|- Arch - No Post-Barrier Return Stack Buffer PBRSB_NO [Capable]
|- Arch - No Gather Data Sampling GDS_NO [ Enable]
|- Arch - No Register File Data Sampling RFDS_NO [Capable]
|- Arch - IPRED disabled for CPL3 IPRED_DIS_U [Capable]
|- Arch - IPRED disabled for CPL0/1/2 IPRED_DIS_S [Capable]
|- Arch - RRSBA disabled for CPL3 RRSBA_DIS_U [Capable]
|- Arch - RRSBA disabled for CPL0/1/2 RRSBA_DIS_S [Capable]
|- Arch - Data Dependent Prefetcher CPL3 DDPD_U_DIS [Capable]
|- Arch - BHI disabled for CPL0/1/2 BHI_DIS_S [ Enable]
|- No MXCSR Configuration Dependent Timing MCDT_NO [ Unable]
|- No MONITOR/UMONITOR mitigation UMON_MITG_NO [ Unable]
|- Overclocking
|- Overclocking Utilized UTILIZED [ Enable]
|- Undervolt Protection UVP [Capable]
|- Overclocking Secure Status UNLOCKED [Capable]
Security Features
|- CPUID Key Locker KL [Capable]
|- AES Key Locker instructions AESKLE [Missing]
|- CET Shadow Stack features CET-SS [Capable]
|- CET Indirect Branch Tracking CET-IBT [Capable]
|- CET Supervisor Shadow Stack CET-SSS [Capable]
|- AES Wide Key Locker instructions WIDE_KL [Capable]
|- Software Guard SGX1 Extensions SGX1 [Missing]
|- Software Guard SGX2 Extensions SGX2 [Missing]
Technologies
|- Data Cache Unit
|- L1 Prefetcher L1 HW <OFF>
|- L1 IP Prefetcher L1 HW IP < ON>
|- L1 Next Page Prefetcher L1 NPP <OFF>
|- L1 Scrubbing L1 Scrubbing <OFF>
|- Cache Prefetchers
|- L2 Prefetcher L2 HW < ON>
|- L2 Adjacent Cache Line Prefetcher L2 HW CL < ON>
|- L2 Adaptive Multipath Probability L2 AMP <OFF>
|- L2 Next Line Prefetcher L2 NLP <OFF>
|- LLC Streamer LLC < ON>
|- System Management Mode SMM-Dual [OFF]
|- Hyper-Threading HTT [OFF]
|- SpeedStep EIST < ON>
|- Dynamic Acceleration IDA [ ON]
|- Turbo Boost Max 3.0 TURBO < ON>
|- Energy Efficiency Optimization EEO <OFF>
|- Race To Halt Optimization R2H <OFF>
|- Watchdog Timer TCO <OFF>
|- Virtualization VMX [OFF]
|- I/O MMU VT-d [ ON]
|- Version [ 4.0]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
|- Volume Management Device VMD [ ON]
|- Gaussian & Neural Accelerator GNA [ ON]
|- Digital Content Protection HDCP [ ON]
|- Image Processing Unit IPU [OFF]
|- Vision Processing Unit VPU [OFF]
|- Overclocking OC [ ON]
Performance Monitoring
|- Version PM [ 5]
|- Counters: General Fixed
| { 6, 0, 0 } x 48 bits 3 x 48 bits
|- Enhanced Halt State C1E <OFF>
|- C1 Auto Demotion C1A < ON>
|- C3 Auto Demotion C3A <OFF>
|- C1 UnDemotion C1U < ON>
|- C3 UnDemotion C3U <OFF>
|- C6 Core Demotion CC6 <OFF>
|- C6 Module Demotion MC6 <OFF>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Hardware Duty Cycling HDC [OFF]
|- Package C-States
|- Configuration Control CONFIG [ LOCK]
|- Lowest C-State LIMIT < C0>
|- I/O MWAIT Redirection IOMWAIT <Disable>
|- Max C-State Inclusion RANGE < C1>
|- Core C-States
|- C-States Base Address BAR [ 0x1814]
|- ACPI Processor C-States _CST [ 2]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 0 2 0 2 0 1 0 1
|- Monitor-Mwait Extensions EMX [Capable]
|- Interrupt Break-Event IBE [Capable]
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Last Level Cache Misses [Capable]
|- Branch Instructions Retired [Capable]
|- Branch Mispredicts Retired [Capable]
|- Top-down slots Counter [Capable]
|- Processor Performance Control _PCT [ Enable]
|- Performance Supported States _PSS [ 0]
|- Performance Present Capabilities _PPC [ 0]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax < 0:100 C>
|- Clock Modulation ODCM <Disable>
|- DutyCycle [ 0.00%]
|- Power Management PWR MGMT [ LOCK]
|- Energy Policy Bias Hint [ 0]
|- Energy Policy HWP EPP < 0>
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Capable]
|- Package Thermal Management PTM [Capable]
|- Thermal Monitor 1 TM1 [ Enable]
|- Thermal Monitor 2 TM2 [Capable]
|- Thermal Design Power TDP [ 125 W]
|- Minimum Power Min [Missing]
|- Maximum Power Max [Missing]
|- Thermal Design Power Package < Enable>
|- Power Limit PL1 < 4095 W>
|- Time Window TW1 < 56 s>
|- Power Limit PL2 < 4095 W>
|- Time Window TW2 < 2 ms>
|- Thermal Design Power Core <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power Uncore <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 976 us>
|- Thermal Design Power DRAM [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 976 us]
|- Thermal Design Power Platform <Disable>
|- Power Limit PL1 < 0 W>
|- Time Window TW1 < 28 s>
|- Power Limit PL2 < 0 W>
|- Time Window TW2 < 976 us>
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Package Thermal Point
|- DTS Threshold #1 Threshold [Missing]
|- DTS Threshold #2 Threshold [Missing]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000061035]
|- Window second [ 0.000976562]
Intel Z790 [7A04]
Controller #0 Dual Channel
Bus Rate 3200 MHz Bus Speed 3216 MHz DDR5 Speed 6433 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 32 39 39 39 89 8 16 32 100 23 136 32 24 2T
#1 32 39 39 39 89 8 16 32 100 23 136 32 24 2T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 16 8 16 16 20 20 22 22 76 52 14 14
#1 16 8 16 16 20 20 22 22 76 52 14 14
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 34 8 16 16 6250 510 940 24 16 2 0
#1 34 8 16 16 6250 510 940 24 16 2 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 131072 1024 32768
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 131072 1024 32768
Where is
Controller #1 DIMMB2?
It did however with AlderLake & DDR4
https://gist.github.com/cyring/f15646816a47a04f8b8f9c3a4cada24c?permalink_comment_id=4454592#gistcomment-4454592
That's why this issue remains opened: I wish new developers could work straight on HW and finalize those IMC decoders.
Also notice that Virtualization section is now showing up in "Technologies"
Thank you for the star
@BugReporterZ Hello,
Can you please pull the latest commits from the develop branch and show the output of corefreq-cli -k -n -B -n -M ?
CC: @paulzzh
@BugReporterZ Hello,
Can you please pull the latest commits from the
developbranch and show the output ofcorefreq-cli -k -n -B -n -M?
I got this:
./corefreq-cli -k -n -B -n -M
Linux:
|- Release [6.9.9-1-default]
|- Version [#1 SMP PREEMPT_DYNAMIC Thu Jul 11 11:31:54 UTC 2024 (8c0f797)]
|- Machine [x86_64]
Memory:
|- Total RAM 65530220 KB
|- Shared RAM 1691920 KB
|- Free RAM 1244324 KB
|- Buffer RAM 672 KB
|- Total High 0 KB
|- Free High 0 KB
Clock Source < tsc>
CPU-Freq driver [ intel_pstate]
Governor [ Missing]
CPU-Idle driver [ intel_idle]
|- Idle Limit [ C10]
|- State POLL C1E C6 C8 C10
|- CPUIDLE MWAIT 0 MWAIT 0 MWAIT 0 MWAIT 0
|- Power -1 0 0 0 0
|- Latency 0 2 220 280 680
|- Residency 0 4 600 800 2000
[ 0] American Megatrends International, LLC.
[ 1] 1.H0
[ 2] 03/29/2024
[ 3] Micro-Star International Co., Ltd.
[ 4] MS-7D25
[ 5] 1.0
[ 6] D---u---s---n-
[ 7] Default string
[ 8] Default string
[ 9] Micro-Star International Co., Ltd.
[10] PRO Z690-A WIFI DDR4(MS-7D25)
[11] 1.0
[12] 0---5---L---0---8-
[13] Number Of Devices:4\Maximum Capacity:134217728 kilobytes
[14] Controller0-DIMMA1\BANK 0
[15] Controller0-DIMMA2\BANK 0
[16] Controller1-DIMMB1\BANK 0
[17] Controller1-DIMMB2\BANK 0
[18] Corsair
[19] Corsair
[20] Corsair
[21] Corsair
[22] CMK32GX4M2D3600C18
[23] CMK32GX4M2D3600C18
[24] CMK32GX4M2D3600C18
[25] CMK32GX4M2D3600C18
Intel Z690 [7A84]
Controller #0 Dual Channel
Bus Rate 3600 MHz Bus Speed 3609 MHz DDR4 Speed 7219 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 18 22 22 22 42 4 9 40 24 12 46 18 7 2T
#1 5 8 8 8 28 4 4 16 14 6 24 6 4 1T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 7 4 12 12 14 15 15 16 36 29 7 7
#1 4 4 4 4 4 4 4 4 4 4 4 4
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 7 4 12 12 14055 630 648 11 4 1 0
#1 4 4 4 4 4100 180 0 4 1 1 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 65536 1024 16384 CMK32GX4M2D3600C18
#1 16 2 65536 1024 16384 CMK32GX4M2D3600C18
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
Controller #1 Dual Channel
Bus Rate 3600 MHz Bus Speed 3609 MHz DDR4 Speed 7219 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 18 22 22 22 42 4 9 40 24 12 46 18 7 2T
#1 5 8 8 8 28 4 4 16 14 6 24 6 4 1T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 7 4 12 12 14 15 15 16 36 29 7 7
#1 4 4 4 4 4 4 4 4 4 4 4 4
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 7 4 12 12 14055 630 648 11 4 1 0
#1 4 4 4 4 4100 180 0 4 1 1 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 65536 1024 16384 CMK32GX4M2D3600C18
#1 16 2 65536 1024 16384 CMK32GX4M2D3600C18
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
I got this:
Thank you
Can you tell if the WR timing of 24 is correct facing its BIOS setting ?
Feel free to post the BIOS screenshot then I can compare all the other timings
Can you please pull the latest commits from the
developbranch and show the output ofcorefreq-cli -k -n -B -n -M?CC: @paulzzh
root@pve:~# corefreq-cli -k -n -B -n -M
Linux:
|- Release [6.8.8-4-pve]
|- Version [#1 SMP PREEMPT_DYNAMIC PMX 6.8.8-4 (2024-07-26T11:15Z)]
|- Machine [x86_64]
Memory:
|- Total RAM 65609688 KB
|- Shared RAM 62128 KB
|- Free RAM 60300304 KB
|- Buffer RAM 131820 KB
|- Total High 0 KB
|- Free High 0 KB
Clock Source < tsc>
CPU-Freq driver [ intel_pstate]
Governor [ Missing]
CPU-Idle driver [ intel_idle]
|- Idle Limit [ C2_ACPI]
|- State POLL C1_ACPI C2_ACPI
|- CPUIDLE ACPI FF ACPI FF
|- Power -1 0 0
|- Latency 0 1 127
|- Residency 0 1 381
[ 0] American Megatrends International, LLC.
[ 1] M.40
[ 2] 04/19/2024
[ 3] Micro-Star International Co., Ltd.
[ 4] MS-7E07
[ 5] 4.0
[ 6] D---u---s---n-
[ 7] Default string
[ 8] Default string
[ 9] Micro-Star International Co., Ltd.
[10] PRO Z790-A MAX WIFI (MS-7E07)
[11] 4.0
[12] 0---7---N---4---5-
[13] Number Of Devices:4\Maximum Capacity:134217728 kilobytes
[14]
[15] Controller0-DIMMA2\BANK 0
[16]
[17] Controller1-DIMMB2\BANK 0
[18]
[19] 0x0B92
[20]
[21] 0x0B92
[22]
[23]
[24]
[25]
Intel Z790 [7A04]
Controller #0 Dual Channel
Bus Rate 3200 MHz Bus Speed 3216 MHz DDR5 Speed 6433 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 32 39 39 39 89 8 16 32 100 23 136 32 24 2T
#1 32 39 39 39 89 8 16 32 100 23 136 32 24 2T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 16 8 16 16 20 20 22 22 76 52 14 14
#1 16 8 16 16 20 20 22 22 76 52 14 14
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 34 8 16 16 6250 510 940 24 16 2 0
#1 34 8 16 16 6250 510 940 24 16 2 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 131072 1024 32768
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 131072 1024 32768
I got this:
Thank you
Can you tell if the
WRtiming of24is correct facing its BIOS setting ?Feel free to post the BIOS screenshot then I can compare all the other timings
@BugReporterZ @paulzzh
My tWR formula is working with DDR4 but not with DDR5
tWR = tWRPRE - tCW - 4
Source code: https://github.com/cyring/CoreFreq/blob/0db6f0a18d3b03a26287fd30d27bb3fd24a2a3c2/x86_64/corefreqd.c#L5623
According to 13th and 14th datasheet, tWRPRE is expressed in tCK delay but in WCK for LPDDR5
I'm reading this
tWRPRE = tWR + tCWL + 8
@paulzzh @BugReporterZ Can you please pull latest commit 36adf0e855ff485a1f219c2927fe924fd168eb6d and post corefreq-cli -M
After pulling and recompiling:
./corefreq-cli -M
Intel Z690 [7A84]
Controller #0 Dual Channel
Bus Rate 3600 MHz Bus Speed 3609 MHz DDR4 Speed 7219 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 18 22 22 22 42 4 9 40 24 12 46 18 7 2T
#1 5 8 8 8 28 4 4 16 14 6 24 6 4 1T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 7 4 12 12 14 15 15 16 36 29 7 7
#1 4 4 4 4 4 4 4 4 4 4 4 4
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 7 4 12 12 14055 630 648 11 4 1 0
#1 4 4 4 4 4100 180 0 4 1 1 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 65536 1024 16384 CMK32GX4M2D3600C18
#1 16 2 65536 1024 16384 CMK32GX4M2D3600C18
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
Controller #1 Dual Channel
Bus Rate 3600 MHz Bus Speed 3609 MHz DDR4 Speed 7219 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 18 22 22 22 42 4 9 40 24 12 46 18 7 2T
#1 5 8 8 8 28 4 4 16 14 6 24 6 4 1T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 7 4 12 12 14 15 15 16 36 29 7 7
#1 4 4 4 4 4 4 4 4 4 4 4 4
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 7 4 12 12 14055 630 648 11 4 1 0
#1 4 4 4 4 4100 180 0 4 1 1 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 65536 1024 16384 CMK32GX4M2D3600C18
#1 16 2 65536 1024 16384 CMK32GX4M2D3600C18
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
WR 100 -> 96
root@pve:~# corefreq-cli -M
Intel Z790 [7A04]
Controller #0 Dual Channel
Bus Rate 3200 MHz Bus Speed 3216 MHz DDR5 Speed 6433 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 32 39 39 39 89 8 16 32 96 23 136 32 24 2T
#1 32 39 39 39 89 8 16 32 96 23 136 32 24 2T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 16 8 16 16 20 20 22 22 76 52 14 14
#1 16 8 16 16 20 20 22 22 76 52 14 14
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 34 8 16 16 6250 510 940 24 16 2 0
#1 34 8 16 16 6250 510 940 24 16 2 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 131072 1024 32768
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 131072 1024 32768
After pulling and recompiling:
Great; no regression on your tWR = 24
I still have no clue how to handle the second channel timings
@paulzzh Hello, The change below is an attempt to fix the second memory controller.
Can you edit code at this line: https://github.com/cyring/CoreFreq/blob/36adf0e855ff485a1f219c2927fe924fd168eb6d/x86_64/corefreqk.c#L6579
And replace function ADL_IMC with this one:
static PCI_CALLBACK ADL_IMC(struct pci_dev *dev)
{ /* Source: 12th Generation Intel Core Processors datasheet, vol 2 */
PCI_CALLBACK rc = 0;
unsigned short mc, cha;
PUBLIC(RO(Proc))->Uncore.CtrlCount = 0;
/* MCHBAR matches bits 41 to 17 ; two MC x 64KB memory space */
for (mc = 0; mc < MC_MAX_CTRL; mc++)
{
rc = ADL_HOST(dev, Query_ADL_IMC, 0x10000, mc);
if ( (PCI_CALLBACK) 0 == rc)
{
if (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADCH.value != 0xffffffff) {
switch (PUBLIC(RO(Proc))->Uncore.MC[mc].ADL.MADCH.DDR_TYPE) {
case 0b01: /* DDR5 */
case 0b10: /* LPDDR5 */
/* if (mc & 1) {
PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount = 0;
} else */{
for (cha = 0; cha < PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount; cha++)
{
PUBLIC(RO(Proc))->Uncore.MC[mc].Channel[cha].ADL.Sched.ReservedBits1=0;
}
}
break;
}
}
if (PUBLIC(RO(Proc))->Uncore.MC[mc].ChannelCount > 0)
{
PUBLIC(RO(Proc))->Uncore.CtrlCount = mc + 1;
}
}
}
return rc;
}
Then rebuild and reload CoreFreq and please post the output of corefreq-cli -M
Then rebuild and reload CoreFreq and please post the output of
corefreq-cli -M
root@pve:~/CoreFreq# corefreq-cli -M
Intel Z790 [7A04]
Controller #0 Dual Channel
Bus Rate 3200 MHz Bus Speed 3216 MHz DDR5 Speed 6433 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 32 39 39 39 89 8 16 32 96 23 136 32 24 2T
#1 32 39 39 39 89 8 16 32 96 23 136 32 24 2T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 16 8 16 16 20 20 22 22 76 52 14 14
#1 16 8 16 16 20 20 22 22 76 52 14 14
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 34 8 16 16 6250 510 940 24 16 2 0
#1 34 8 16 16 6250 510 940 24 16 2 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 131072 1024 32768
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 131072 1024 32768
Controller #1 Dual Channel
Bus Rate 3200 MHz Bus Speed 3216 MHz DDR5 Speed 6433 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 32 39 39 39 89 8 16 32 96 23 136 32 24 2T
#1 32 39 39 39 89 8 16 32 96 23 136 32 24 2T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 16 8 16 16 20 20 22 22 76 52 14 14
#1 16 8 16 16 20 20 22 22 76 52 14 14
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 34 8 16 16 6250 510 940 24 16 2 0
#1 34 8 16 16 6250 510 940 24 16 2 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 131072 1024 32768
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1 16 2 131072 1024 32768
I'm getting this.
./corefreq-cli -M
Intel Z690 [7A84]
Controller #0 Dual Channel
Bus Rate 3600 MHz Bus Speed 3609 MHz DDR4 Speed 7219 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 18 22 22 22 42 4 9 40 24 12 46 18 7 2T
#1 5 8 8 8 28 4 4 16 14 6 24 6 4 1T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 7 4 12 12 14 15 15 16 36 29 7 7
#1 4 4 4 4 4 4 4 4 4 4 4 4
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 7 4 12 12 14055 630 648 11 4 1 0
#1 4 4 4 4 4100 180 0 4 1 1 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 65536 1024 16384 CMK32GX4M2D3600C18
#1 16 2 65536 1024 16384 CMK32GX4M2D3600C18
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
Controller #1 Dual Channel
Bus Rate 3600 MHz Bus Speed 3609 MHz DDR4 Speed 7219 MT/s
Cha CL RCDr RCDw RP RAS RRDs RRDl FAW WR RTPr WTPr CWL CKE CMD
#0 18 22 22 22 42 4 9 40 24 12 46 18 7 2T
#1 5 8 8 8 28 4 4 16 14 6 24 6 4 1T
sgRR dgRR drRR ddRR sgRW dgRW drRW ddRW sgWR dgWR drWR ddWR
#0 7 4 12 12 14 15 15 16 36 29 7 7
#1 4 4 4 4 4 4 4 4 4 4 4 4
sgWW dgWW drWW ddWW REFI RFC XS XP CPDED GEAR ECC
#0 7 4 12 12 14055 630 648 11 4 1 0
#1 4 4 4 4 4100 180 0 4 1 1 0
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 2 65536 1024 16384 CMK32GX4M2D3600C18
#1 16 2 65536 1024 16384 CMK32GX4M2D3600C18
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0
#1
I'm getting this.
Thank you. So for your DDR4 case, code change does not make any difference
Issue happens with DDR5 where DIMMs are duplicated among channel 0 and 1 (@paulzzh)