CoreFreq
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Published
20 hours ago •
cyring
cyring
[WANTED] AMD/Zen3: Cezanne, Rembrandt, Milan, Chagall
Hello
The targeted processors have a CPUID signature among the following:
| Architecture | CPUID | Misc | Support | Specs |
|---|---|---|---|---|
[Zen3/Vermeer] |
AF_21h |
Ryzen 5950X | DONE | 56214-B0-PUB_3.05_PPR.pdf |
[Zen3/Cezanne] |
AF_50h |
Ryzen APU | DONE | 56569-A1-PUB_3.03_ppr.pdf |
[EPYC/Milan] |
AF_01h |
Genesis[GN] | UNKNOWN | - |
[EPYC/Milan-X] |
AF_01h |
EPYC | UNKNOWN | - |
[Zen3/Chagall] |
AF_08h |
Ryzen Threadripper | UNKNOWN | - |
[Zen3/Badami] |
AF_30h |
[BA] - 7 nm - SVR | UNKNOWN | - |
[Zen3+ Rembrandt] |
AF_44h |
Ryzen 6xxxH | UNKNOWN | - |
Can anyone give a try to the develop branch of CoreFreq next version 1.91.5 and post the output of the Client (corefreq-cli -s -n -m -n -M -n -B -n -k -n -C 1)
Thanks for any help
Hi,
This is the output of the program on my Ryzen 7 5800H
Processor [AMD Ryzen 7 5800H with Radeon Graphics]
|- Architecture [Zen3/Cezanne]
|- Vendor ID [AuthenticAMD]
|- Microcode [0x0a50000c]
|- Signature [ AF_50]
|- Stepping [ 0]
|- Online CPU [ 16/ 16]
|- Base Clock [ 99.809]
|- Frequency (MHz) Ratio
Min 1197.70 < 12 >
Max 3193.88 < 32 >
|- Factory [100.000]
3200 [ 32 ]
|- Performance
|- P-State
TGT 3193.88 < 32 >
|- Turbo Boost [ LOCK]
XFR 4391.58 [ 44 ]
CPB 4391.58 [ 44 ]
1C 1297.51 < 13 >
2C 1197.70 < 12 >
|- Uncore [ LOCK]
|- TDP Level [ 0:0 ]
|- Programmable [ LOCK]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] AVX-VNNI-VEX [N] AVX-FP128 [N] AVX-FP256 [Y]
|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- MMX/Ext [Y/Y] MON/MWAITX [Y/Y] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] RDPID [N] UMIP [N]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- 100 MHz multiplier Control 100MHzSteps [Missing]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- Core Multi-Processing CMP Legacy [Capable]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Collaborative Processor Performance Control CPPC [Capable]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Missing]
|- CPL Qualified Debug Store DS-CPL [Missing]
|- 64-Bit Debug Store DTES64 [Missing]
|- Fast Short REP MOVSB FSRM [Capable]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA | FMA4 [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Hardware P-state control HwP [Capable]
|- Instruction Based Sampling IBS [Capable]
|- Instruction INVLPGB INVLPGB [Missing]
|- Instruction INVPCID INVPCID [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Memory Bandwidth Enforcement MBE [Capable]
|- Machine-Check Architecture MCA [Capable]
|- Instruction MCOMMIT MCOMMIT [Missing]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Missing]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Missing]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Resource Director Technology/PQE RDT-A [Capable]
|- Resource Director Technology/PQM RDT-M [Capable]
|- Read Processor Register at User level RDPRU [Capable]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Missing]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Missing]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Missing]
|- Extended xAPIC Support x2APIC [ x2APIC]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Capable]
|- IBRS Always-On preferred by processor [Missing]
|- IBRS preferred over software solution [Capable]
|- IBRS provides same speculation limits [Capable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [ Enable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- SSBD use VIRT SPEC_CTRL register [Missing]
|- SSBD not needed on this processor [Missing]
|- Architectural - Predictive Store Forwarding PSFD [Capable]
Technologies
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- L2 Prefetcher L2 HW < ON>
|- System Management Mode SMM-Lock [ ON]
|- Simultaneous Multithreading SMT [ ON]
|- PowerNow! CnQ [OFF]
|- Core C-States CCx [ ON]
|- Core Performance Boost CPB < ON>
|- Watchdog Timer WDT < ON>
|- Virtualization SVM [ ON]
|- I/O MMU AMD-V [ ON]
|- Version [ 0.1]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [N/A]
|- Counters: General Fixed
| { 6, 6, 4 } x 48 bits 3 x 64 bits
|- Enhanced Halt State C1E <OFF>
|- C2 UnDemotion C2U < ON>
|- C3 UnDemotion C3U < ON>
|- Core C6 State CC6 < ON>
|- Package C6 State PC6 < ON>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Collaborative Processor Performance Control CPPC <OFF>
|- Capabilities (MHz) Ratio
Lowest AUTO [ 0 ]
Efficient AUTO [ 0 ]
Guaranteed AUTO [ 0 ]
Highest AUTO [ 0 ]
|- Core C-States
|- C-States Base Address BAR [ 0x413 ]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 1 1 0 0 0 0 0 0
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Global Time Stamp Counter [Missing]
|- Data Fabric Performance Counter [Capable]
|- Core Performance Counter [Capable]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax [ 49: 0 C]
|- CPPC Energy Preference CPPC [Capable]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Missing]
|- Package Thermal Management PTM [Missing]
|- Thermal Monitor 1 TTP [ Enable]
|- Thermal Monitor 2 HTC [ Enable]
|- Thermal Design Power TDP [Missing]
|- Minimum Power Min [Missing]
|- Maximum Power Max [ 128 W]
|- Thermal Design Power Package [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Power Limit PL2 [ 0 W]
|- Time Window TW2 [ 0 ns]
|- Thermal Design Power Core [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Uncore [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power DRAM [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Platform [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Power Limit PL2 [ 0 W]
|- Time Window TW2 [ 0 ns]
|- Package Power Tracking PPT [Missing]
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- Package Thermal Point
|- Thermal Monitor Trip Limit [ 125 C]
|- HTC Temperature Limit Limit [ 127 C]
|- HTC Temperature Hysteresis Threshold [ 2 C]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000015259]
|- Window second [ 0.000976562]
CPU Pkg Apic Core/Thread Caches (w)rite-Back (i)nclusive
# ID ID CCD CCX ID/ID L1-Inst Way L1-Data Way L2 Way L3 Way
000:BSP 0 0 0 0 0 32 8 32 8 512 8 i 16384 16w
001: 0 1 0 0 0 1 32 8 32 8 512 8 i 16384 16w
002: 0 2 0 0 1 0 32 8 32 8 512 8 i 16384 16w
003: 0 3 0 0 1 1 32 8 32 8 512 8 i 16384 16w
004: 0 4 0 0 2 0 32 8 32 8 512 8 i 16384 16w
005: 0 5 0 0 2 1 32 8 32 8 512 8 i 16384 16w
006: 0 6 0 0 3 0 32 8 32 8 512 8 i 16384 16w
007: 0 7 0 0 3 1 32 8 32 8 512 8 i 16384 16w
008: 0 8 0 1 4 0 32 8 32 8 512 8 i 16384 16w
009: 0 9 0 1 4 1 32 8 32 8 512 8 i 16384 16w
010: 0 10 0 1 5 0 32 8 32 8 512 8 i 16384 16w
011: 0 11 0 1 5 1 32 8 32 8 512 8 i 16384 16w
012: 0 12 0 1 6 0 32 8 32 8 512 8 i 16384 16w
013: 0 13 0 1 6 1 32 8 32 8 512 8 i 16384 16w
014: 0 14 0 1 7 0 32 8 32 8 512 8 i 16384 16w
015: 0 15 0 1 7 1 32 8 32 8 512 8 i 16384 16w
AuthenticAMD [ 0]
Controller #0 Disabled
AF_50h.txt lscpi.txt zencli.txt
Hi,
This is the output of the program on my Ryzen 7 5800H
Thank you very much.
zencli is decoding 2 DIMMs 4GB each. Is this what your setup has ?
Hi, This is the output of the program on my Ryzen 7 5800H
Thank you very much.
zencli is decoding 2 DIMMs 4GB each. Is this what your setup has ?
no, my machine is configured with 2x8GB module dmidecode.txt
Hi, This is the output of the program on my Ryzen 7 5800H
Thank you very much. zencli is decoding 2 DIMMs 4GB each. Is this what your setup has ?
no, my machine is configured with 2x8GB module dmidecode.txt
Can you pull, build and run the latest develop branch ?
Last commit is removing the Experimental mode to query the UMC Memory Controller
The output I would like to examine:
corefreq-cli -M -n -B -n -k -n -C 1
Hi, This is the output of the program on my Ryzen 7 5800H
Thank you very much. zencli is decoding 2 DIMMs 4GB each. Is this what your setup has ?
no, my machine is configured with 2x8GB module dmidecode.txt
Can you pull, build and run the latest
developbranch ? Last commit is removing the Experimental mode to query the UMC Memory ControllerThe output I would like to examine:
corefreq-cli -M -n -B -n -k -n -C 1
Hi This is the output using the latest develop branch build
AuthenticAMD [ 0]
Controller #0 Disabled
[ 0] American Megatrends International, LLC.
[ 1] E158LAMS.108
[ 2] 04/07/2022
[ 3] Micro-Star International Co., Ltd.
[ 4] Alpha 15 B5EEK
[ 5] REV:1.0
[ 6] 9---5---2---Z---0---5
[ 7] 158L.1
[ 8] Alpha
[ 9] Micro-Star International Co., Ltd.
[10] MS-158L
[11] REV:1.0
[12] B---0---4---8-
[13] Number Of Devices:2\Maximum Capacity:33554432 bytes
[14] DIMM 0\P0 CHANNEL A
[15] DIMM 0\P0 CHANNEL B
[16]
[17]
[18] Samsung
[19] Samsung
[20]
[21]
[22] M471A1K43EB1-CWE
[23] M471A1K43EB1-CWE
[24]
[25]
Linux:
|- Release [5.18.16]
|- Version [#1 SMP PREEMPT_DYNAMIC Wed Aug 3 07:13:22 CDT 2022]
|- Machine [x86_64]
Memory:
|- Total RAM 15743348 KB
|- Shared RAM 193632 KB
|- Free RAM 3455900 KB
|- Buffer RAM 152156 KB
|- Total High 0 KB
|- Free High 0 KB
Clock Source < tsc>
CPU-Freq driver [ acpi-cpufreq]
Governor [ performance]
CPU-Idle driver [ acpi_idle]
|- Idle Limit [ C3]
|- State POLL C1 C2 C3
|- CPUIDLE ACPI FF ACPI IO ACPI IO
|- Power -1 0 0 0
|- Latency 0 1 18 350
|- Residency 0 2 36 700
CPU Freq(MHz) VID Vcore TMP(C) Accumulator Energy(J) Power(W)
000 31.90 125 0.7688 47 000000000000010449 0.159439087 0.159439087
001 47.25 122 0.7875 47 000000000000000000 0.000000000 0.000000000
002 51.03 122 0.7875 47 000000000000006615 0.100936890 0.100936890
003 16.07 122 0.7875 47 000000000000000000 0.000000000 0.000000000
004 88.24 121 0.7937 47 000000000000009005 0.137405396 0.137405396
005 17.99 121 0.7937 47 000000000000000000 0.000000000 0.000000000
006 36.43 122 0.7875 47 000000000000011955 0.182418823 0.182418823
007 34.50 122 0.7875 47 000000000000000000 0.000000000 0.000000000
008 46.83 121 0.7937 47 000000000000007135 0.108871460 0.108871460
009 29.55 121 0.7937 47 000000000000000000 0.000000000 0.000000000
010 42.10 122 0.7875 47 000000000000005993 0.091445923 0.091445923
011 24.54 122 0.7875 47 000000000000000000 0.000000000 0.000000000
012 25.71 121 0.7937 47 000000000000007994 0.121978760 0.121978760
013 13.23 121 0.7937 47 000000000000000000 0.000000000 0.000000000
014 54.20 112 0.8500 47 000000000000016453 0.251052856 0.251052856
015 152.56 112 0.8500 47 000000000000000000 0.000000000 0.000000000
Package Cores Uncore Memory Platform
Energy(J): 10.459701538 1.457260132 6.430450439 0.000000000 0.000000000
Power(W) : 10.459701538 1.457260132 6.430450439 0.000000000 0.000000000
kernel load command:
@nhattu1986 Thanks. Something I don't understand with this APU which queries no UMC data from driver.
@nhattu1986
Can you try UMC again but make sure without the Experimental parameter.
Like:
insmod corefreqk.ko
corefreqd
corefreq-cli -M
@nhattu1986
Can you try UMC again but make sure without the
Experimentalparameter.Like:
insmod corefreqk.ko corefreqdcorefreq-cli -M
Hi,
Running the kernel module without parameter still not yield any output
nhattu@a15:/tmp/corefreq-develop$ corefreq-cli -M
AuthenticAMD [ 0]
Controller #0 Disabled
@nhattu1986 Can you try UMC again but make sure without the
Experimentalparameter. Like:insmod corefreqk.ko corefreqdcorefreq-cli -MHi,
Running the kernel module without parameter still not yield any output
nhattu@a15:/tmp/corefreq-develop$ corefreq-cli -M AuthenticAMD [ 0] Controller #0 Disabled
I have to put traces in driver to follow the callflow.
EDIT: was corefreq.ko of development version also installed into /lib/module/5.18.16/extra ?
@nhattu1986 Can you please run the attached archive ?
To avoid any API conflict, make sure any other versions of CoreFreq is unloaded/uninstalled/removed from your disk. Only this archive has to be insmod from its own directory.
Your kernel log should dump some traces as below:
CoreFreq: AMD_DataFabric_Cezanne(00000000dcb8cb06)
CoreFreq: AMD_17h_DataFabric(00000000dcb8cb06,1,24)
CoreFreq: AMD_17h_DataFabric(): CtrlCount[1]
CoreFreq: AMD_17h_DataFabric(): ChannelCnt[0}
CoreFreq: AMD_17h_DataFabric(): SDP_CTRL passed
CoreFreq: AMD_17h_DataFabric(): ChannelCnt[1}
CoreFreq: AMD_17h_DataFabric(): SDP_CTRL passed
CoreFreq: AMD_17h_DataFabric(): ChannelCnt[2}
CoreFreq: AMD_17h_DataFabric(): ChannelCnt[3}
CoreFreq: AMD_17h_DataFabric(): ChannelCnt[4}
CoreFreq: AMD_17h_DataFabric(): ChannelCnt[5}
CoreFreq: AMD_17h_DataFabric(): ChannelCnt[6}
CoreFreq: AMD_17h_DataFabric(): ChannelCnt[7}
@nhattu1986 Can you please run the attached archive ?
To avoid any API conflict, make sure any other versions of CoreFreq is unloaded/uninstalled/removed from your disk. Only this archive has to be
insmodfrom its own directory.Your kernel log should dump some traces as below:
CoreFreq: AMD_DataFabric_Cezanne(00000000dcb8cb06) CoreFreq: AMD_17h_DataFabric(00000000dcb8cb06,1,24) CoreFreq: AMD_17h_DataFabric(): CtrlCount[1] CoreFreq: AMD_17h_DataFabric(): ChannelCnt[0} CoreFreq: AMD_17h_DataFabric(): SDP_CTRL passed CoreFreq: AMD_17h_DataFabric(): ChannelCnt[1} CoreFreq: AMD_17h_DataFabric(): SDP_CTRL passed CoreFreq: AMD_17h_DataFabric(): ChannelCnt[2} CoreFreq: AMD_17h_DataFabric(): ChannelCnt[3} CoreFreq: AMD_17h_DataFabric(): ChannelCnt[4} CoreFreq: AMD_17h_DataFabric(): ChannelCnt[5} CoreFreq: AMD_17h_DataFabric(): ChannelCnt[6} CoreFreq: AMD_17h_DataFabric(): ChannelCnt[7}
Hi
This is the kernel output:
[47012.082458] CoreFreq(2:3:-1): Processor [ AF_50] Architecture [Zen3/Cezanne] SMT [16/16]
[47012.082545] CoreFreq: AMD_DataFabric_Cezanne(00000000339291a7)
[47012.082548] CoreFreq: AMD_17h_DataFabric(00000000339291a7,1,24)
[47012.082552] CoreFreq: AMD_17h_DataFabric(): CtrlCount[1]
[47012.082553] CoreFreq: AMD_17h_DataFabric(): ChannelCnt[0}
[47012.082558] CoreFreq: AMD_17h_DataFabric(): SDP_CTRL passed
[47012.082635] CoreFreq: AMD_17h_DataFabric(): ChannelCnt[1}
[47012.082639] CoreFreq: AMD_17h_DataFabric(): SDP_CTRL passed
[47012.082694] CoreFreq: AMD_17h_DataFabric(): ChannelCnt[2}
[47012.082698] CoreFreq: AMD_17h_DataFabric(): ChannelCnt[3}
[47012.082702] CoreFreq: AMD_17h_DataFabric(): ChannelCnt[4}
[47012.082705] CoreFreq: AMD_17h_DataFabric(): ChannelCnt[5}
[47012.082709] CoreFreq: AMD_17h_DataFabric(): ChannelCnt[6}
[47012.082712] CoreFreq: AMD_17h_DataFabric(): ChannelCnt[7}
@nhattu1986 Hello, can you pull latest develop branch ?
I have fixed missing Device IDs in Daemon.
I would like the output corefreq-cli -s -n -M
EDIT: expected topology (according to M471A1K43EB1-CWE specs)
Bank Rank Rows Columns Memory Size (MB)
16 1 65536 1024 8192
Hi @cyring
I'm building the latest develop branch and got the output:
Processor [AMD Ryzen 7 5800H with Radeon Graphics]
|- Architecture [Zen3/Cezanne]
|- Vendor ID [AuthenticAMD]
|- Microcode [0x0a50000c]
|- Signature [ AF_50]
|- Stepping [ 0]
|- Online CPU [ 16/ 16]
|- Base Clock [ 99.789]
|- Frequency (MHz) Ratio
Min 1197.47 < 12 >
Max 3193.25 < 32 >
|- Factory [100.000]
3200 [ 32 ]
|- Performance
|- P-State
TGT 1197.47 < 12 >
|- Turbo Boost [ LOCK]
XFR 4390.72 [ 44 ]
CPB 4390.72 [ 44 ]
1C 1297.26 < 13 >
2C 1197.47 < 12 >
|- Uncore [ LOCK]
|- TDP Level [ 0:0 ]
|- Programmable [ LOCK]
Instruction Set Extensions
|- 3DNow!/Ext [N/N] ADX [Y] AES [Y] AVX/AVX2 [Y/Y]
|- AVX512-F [N] AVX512-DQ [N] AVX512-IFMA [N] AVX512-PF [N]
|- AVX512-ER [N] AVX512-CD [N] AVX512-BW [N] AVX512-VL [N]
|- AVX512-VBMI [N] AVX512-VBMI2 [N] AVX512-VNNI [N] AVX512-ALG [N]
|- AVX512-VPOP [N] AVX512-VNNIW [N] AVX512-FMAPS [N] AVX512-VP2I [N]
|- AVX512-BF16 [N] AVX-VNNI-VEX [N] AVX-FP128 [N] AVX-FP256 [Y]
|- BMI1/BMI2 [Y/Y] CLWB [Y] CLFLUSH [Y] CLFLUSH-OPT [Y]
|- CLAC-STAC [Y] CMOV [Y] CMPXCHG8B [Y] CMPXCHG16B [Y]
|- F16C [Y] FPU [Y] FXSR [Y] LAHF-SAHF [Y]
|- MMX/Ext [Y/Y] MON/MWAITX [Y/Y] MOVBE [Y] PCLMULQDQ [Y]
|- POPCNT [Y] RDRAND [Y] RDSEED [Y] RDTSCP [Y]
|- SEP [Y] SHA [Y] SSE [Y] SSE2 [Y]
|- SSE3 [Y] SSSE3 [Y] SSE4.1/4A [Y/Y] SSE4.2 [Y]
|- SERIALIZE [N] SYSCALL [Y] RDPID [N] UMIP [N]
Features
|- 1 GB Pages Support 1GB-PAGES [Capable]
|- 100 MHz multiplier Control 100MHzSteps [Missing]
|- Advanced Configuration & Power Interface ACPI [Capable]
|- Advanced Programmable Interrupt Controller APIC [Capable]
|- APIC Timer Invariance ARAT [Capable]
|- Core Multi-Processing CMP Legacy [Capable]
|- L1 Data Cache Context ID CNXT-ID [Missing]
|- Collaborative Processor Performance Control CPPC [Capable]
|- Direct Cache Access DCA [Missing]
|- Debugging Extension DE [Capable]
|- Debug Store & Precise Event Based Sampling DS, PEBS [Missing]
|- CPL Qualified Debug Store DS-CPL [Missing]
|- 64-Bit Debug Store DTES64 [Missing]
|- Fast Short REP MOVSB FSRM [Capable]
|- Fast-String Operation ERMS [Capable]
|- Fused Multiply Add FMA | FMA4 [Capable]
|- Hardware Lock Elision HLE [Missing]
|- Hardware P-state control HwP [Capable]
|- Instruction Based Sampling IBS [Capable]
|- Instruction INVLPGB INVLPGB [Missing]
|- Instruction INVPCID INVPCID [Capable]
|- Long Mode 64 bits IA64 | LM [Capable]
|- LightWeight Profiling LWP [Missing]
|- Memory Bandwidth Enforcement MBE [Capable]
|- Machine-Check Architecture MCA [Capable]
|- Instruction MCOMMIT MCOMMIT [Missing]
|- Memory Protection Extensions MPX [Missing]
|- Model Specific Registers MSR [Capable]
|- Memory Type Range Registers MTRR [Capable]
|- No-Execute Page Protection NX [Capable]
|- OS-Enabled Ext. State Management OSXSAVE [Capable]
|- Physical Address Extension PAE [Capable]
|- Page Attribute Table PAT [Capable]
|- Pending Break Enable PBE [Missing]
|- Process Context Identifiers PCID [Missing]
|- Perfmon and Debug Capability PDCM [Missing]
|- Page Global Enable PGE [Capable]
|- Page Size Extension PSE [Capable]
|- 36-bit Page Size Extension PSE36 [Capable]
|- Processor Serial Number PSN [Missing]
|- Resource Director Technology/PQE RDT-A [Capable]
|- Resource Director Technology/PQM RDT-M [Capable]
|- Read Processor Register at User level RDPRU [Capable]
|- Restricted Transactional Memory RTM [Missing]
|- Safer Mode Extensions SMX [Missing]
|- Self-Snoop SS [Missing]
|- Supervisor-Mode Access Prevention SMAP [Capable]
|- Supervisor-Mode Execution Prevention SMEP [Capable]
|- Time Stamp Counter TSC [Invariant]
|- Time Stamp Counter Deadline TSC-DEADLINE [Missing]
|- TSX Force Abort MSR Register TSX-ABORT [Missing]
|- TSX Suspend Load Address Tracking TSX-LDTRK [Missing]
|- User-Mode Instruction Prevention UMIP [Missing]
|- Virtual Mode Extension VME [Capable]
|- Virtual Machine Extensions VMX [Missing]
|- Extended xAPIC Support x2APIC [ x2APIC]
|- XSAVE/XSTOR States XSAVE [Capable]
|- xTPR Update Control xTPR [Missing]
Mitigation mechanisms
|- Indirect Branch Restricted Speculation IBRS [Capable]
|- IBRS Always-On preferred by processor [Missing]
|- IBRS preferred over software solution [Capable]
|- IBRS provides same speculation limits [Capable]
|- Indirect Branch Prediction Barrier IBPB [Capable]
|- Single Thread Indirect Branch Predictor STIBP [ Enable]
|- Speculative Store Bypass Disable SSBD [Capable]
|- SSBD use VIRT SPEC_CTRL register [Missing]
|- SSBD not needed on this processor [Missing]
|- Architectural - Predictive Store Forwarding PSFD [Capable]
Technologies
|- Data Cache Unit
|- L1 Prefetcher L1 HW < ON>
|- L2 Prefetcher L2 HW < ON>
|- System Management Mode SMM-Lock [ ON]
|- Simultaneous Multithreading SMT [ ON]
|- PowerNow! CnQ [OFF]
|- Core C-States CCx [ ON]
|- Core Performance Boost CPB < ON>
|- Watchdog Timer WDT < ON>
|- Virtualization SVM [ ON]
|- I/O MMU AMD-V [ ON]
|- Version [ 0.1]
|- Hypervisor [OFF]
|- Vendor ID [ N/A]
Performance Monitoring
|- Version PM [N/A]
|- Counters: General Fixed
| { 6, 6, 4 } x 48 bits 3 x 64 bits
|- Enhanced Halt State C1E <OFF>
|- C2 UnDemotion C2U < ON>
|- C3 UnDemotion C3U < ON>
|- Core C6 State CC6 <OFF>
|- Package C6 State PC6 < ON>
|- Legacy Frequency ID control FID [OFF]
|- Legacy Voltage ID control VID [OFF]
|- P-State Hardware Coordination Feedback MPERF/APERF [ ON]
|- Collaborative Processor Performance Control CPPC <OFF>
|- Capabilities (MHz) Ratio
Lowest AUTO [ 0 ]
Efficient AUTO [ 0 ]
Guaranteed AUTO [ 0 ]
Highest AUTO [ 0 ]
|- Core C-States
|- C-States Base Address BAR [ 0x413 ]
|- MONITOR/MWAIT
|- State index: #0 #1 #2 #3 #4 #5 #6 #7
|- Sub C-State: 1 1 0 0 0 0 0 0
|- Core Cycles [Capable]
|- Instructions Retired [Capable]
|- Reference Cycles [Capable]
|- Last Level Cache References [Capable]
|- Global Time Stamp Counter [Missing]
|- Data Fabric Performance Counter [Capable]
|- Core Performance Counter [Capable]
Power, Current & Thermal
|- Temperature Offset:Junction TjMax [ 49: 0 C]
|- CPPC Energy Preference CPPC [Capable]
|- Digital Thermal Sensor DTS [Capable]
|- Power Limit Notification PLN [Missing]
|- Package Thermal Management PTM [Missing]
|- Thermal Monitor 1 TTP [ Enable]
|- Thermal Monitor 2 HTC [ Enable]
|- Thermal Design Power TDP [Missing]
|- Minimum Power Min [Missing]
|- Maximum Power Max [ 128 W]
|- Thermal Design Power Package [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Power Limit PL2 [ 0 W]
|- Time Window TW2 [ 0 ns]
|- Thermal Design Power Core [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Uncore [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power DRAM [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Thermal Design Power Platform [Disable]
|- Power Limit PL1 [ 0 W]
|- Time Window TW1 [ 0 ns]
|- Power Limit PL2 [ 0 W]
|- Time Window TW2 [ 0 ns]
|- Package Power Tracking PPT [Missing]
|- Electrical Design Current EDC [Missing]
|- Thermal Design Current TDC [Missing]
|- Core Thermal Point
|- Package Thermal Point
|- Thermal Monitor Trip Limit [ 125 C]
|- HTC Temperature Limit Limit [ 127 C]
|- HTC Temperature Hysteresis Threshold [ 2 C]
|- Units
|- Power watt [ 0.125000000]
|- Energy joule [ 0.000015259]
|- Window second [ 0.000976562]
Zen UMC [166A]
Controller #0 Dual Channel
Bus Rate 1600 MHz Bus Speed 1596 MHz DDR4 Speed 3193 MT/s
Cha CL RCDr RCDw RP RAS RC RRDs RRDl FAW WTRs WTRl WR clRR clWW
#0 22 22 22 22 52 74 4 8 34 4 12 24 5 5
#1 22 22 22 22 52 74 4 8 34 4 12 24 5 5
CWL RTP RdWr WrRd scWW sdWW ddWW scRR sdRR ddRR drRR drWW drWR drRRD
#0 18 12 11 1 1 6 6 1 4 4 0 0 0 0
#1 18 12 10 1 1 6 6 1 4 4 0 0 0 0
REFI RFC1 RFC2 RFC4 RCPB RPPB BGS:Alt Ban Page CKE CMD GDM ECC
#0 12480 560 416 256 0 0 OFF OFF R1W1 0 9 1T ON 0
#1 12480 560 416 256 0 0 OFF OFF R1W1 0 9 1T ON 0
MRD:PDA MOD:PDA WRMPR STAG PDM RDDATA WRD WRL RDL XS XP CPDED
#0 8 16 24 24 24 9 1:P:1 17 2 13 24 576 10 4
#1 8 16 24 24 24 9 1:P:1 17 2 13 24 576 10 4
DIMM Geometry for channel #0
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 1 65536 1024 8192 M471A1K43EB1-CWE
#1
DIMM Geometry for channel #1
Slot Bank Rank Rows Columns Memory Size (MB)
#0 16 1 65536 1024 8192 M471A1K43EB1-CWE
#1
Hi @cyring
I'm building the latest develop branch and got the output:
Thanks a lot for your contribution.
Wiki CPU support page is updated with Ryzen 7 5800H
This development is also available in the CoreFreq ISO image @ www.cyring.fr
Other features can also be tested with Cezanne:
-
HSMP enablementfrom theSettingsmenu -
CPPCfrom thePerformance Monitoringmenu