CyrIng

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I think Genoa and Zen4/Hawk Point (#84) are missing the temperature for the same reason: no thermal register known.

Meanwhile I can fix the voltage Vcore if you provide me the CLI output requested above.

Can you please pull [`develop`](https://github.com/cyring/CoreFreq/tree/develop) branch and test temperature ?

Which temperature are we reading when System is idling ? ``` corefreq-cli -C 1 -n -c 1 ```

First Gen needed an temperature offset. Perhaps same with Genoa. Can you compile my SMU tool [zencli](https://github.com/cyring/Tips/blob/master/C/zencli.c) ? ```sh cc zencli.c -o zencli ``` As root, you will peek the...

> The Mhz reported, are relative to what ? Those are cycles counted by hardware When no activity they fall down to no cycle ![2024-03-18-013252_644x473_scrot](https://github.com/cyring/CoreFreq/assets/11563789/b6c237e3-427e-4c74-abcb-1c83fb252b53) Relative comes from the Intel...

Can you also dump the CCD range ? ```sh ## per CCD zencli smu 0x59954 zencli smu 0x59958 zencli smu 0x5995C zencli smu 0x59960 zencli smu 0x59964 zencli smu 0x59968...

I see, `k10temp` found them at offset 0x300 of 0x59800 https://elixir.bootlin.com/linux/latest/source/drivers/hwmon/k10temp.c#L475 So SMU address is 0x59B00 + (CCD number * 4)

Fortunately thermal function was already made for Raphael. Genoa is now pointing to it. Please pull and test latest commit 7c926afda6ac5c890373dccebc08d774fc136dfa from `develop`

It may be a wrong Register address Still based on `develop` branch, can you edit the header file at that line: https://github.com/cyring/CoreFreq/blob/87344fae6395c7d3d5dd6b7b0876a6ee3aae413d/x86_64/amd_reg.h#L208 and replace code with this one: ```c #define...