CyrIng

> > Hello, > > Since commit [62e8372](https://github.com/cyring/CoreFreq/commit/62e8372a9ed311f979efa201a2b91652e12d4ff2) you can try the Memory Controller decoding and post here the output of `/corefreq-cli -M` > > `corefreq-cli -M` > > ```...

Because DIMM are of DDR5, we will try another UMC query. Based on latest commit: 1. edit `corefreqk.h` https://github.com/cyring/CoreFreq/blob/ac246cdc7cd1bee2dde1218791e64c4f6fcc1f02/x86_64/corefreqk.h#L3171 2. change for the Rambrandt decoder ```c { PCI_VDEVICE(AMD, DID_AMD_17H_JUPITER_DF_UMC), .driver_data...

```console CPU #0 function EAX EBX ECX EDX |- 80000008:00000000 00003030 090cf657 00007007 00010000 ``` Availability of Hardware CPPC Registers is confirmed by [bit 27](https://github.com/cyring/CoreFreq/blob/ac246cdc7cd1bee2dde1218791e64c4f6fcc1f02/x86_64/coretypes.h#L1873C8-L1873C8) of EBX We are dumping...

> hmm no change. > > journal logs https://gist.github.com/wallentx/58ff422e80b21a13d822909f9ea414bb It's hard to debug from here; the fact that `zencli umc` found some meaningful values ...

Pre-release on going if you wish to complete your issue. https://github.com/cyring/CoreFreq/discussions/472

 J3455 has crashed when reading MSR `0x64c` in register `RCX` I have to search if this [`MSR_TURBO_ACTIVATION_RATIO`](https://github.com/cyring/CoreFreq/blob/6bbbb752d0efcfcf42daffbcc78ad38640acbade/x86_64/intel_reg.h#L177) is allowed or not in architecture. Perhaps an exception model. ~~Meanwhile can...

``` Qnap kernel: smpboot: CPU0: Intel(R) Celeron(R) CPU J3455 @ 1.50GHz (family: 0x6, model: 0x5c, stepping: 0x9) ``` _CoreFreq_ will identify family as [`Goldmont(06_5Ch)`](https://github.com/cyring/CoreFreq/blob/6bbbb752d0efcfcf42daffbcc78ad38640acbade/x86_64/corefreqk.h#L1776) But architecture says the MSR is...

 As specified by the [ARK](https://ark.intel.com/content/www/us/en/ark/products/95594/intel-celeron-processor-j3455-2m-cache-up-to-2-3-ghz.html) for Celeron J3455, if processor is not capable of Intel Turbo Boost Technology, there is **no reason** to trigger MSR Turbo Activation Ratio

> This is `lscpu` from the `Diagnostics.zip`: [lscpu.txt](https://github.com/cyring/CoreFreq/files/14351028/lscpu.txt) Thank you. Fix commit 91ed011ef1f99b416b57735ddcf8fc66a35aea7f is ready in branch `develop`. Can you please provide a testing version to User ?

> See his comment [here](https://forums.unraid.net/topic/109314-plugin-corefreq/?do=findComment&comment=1374676). > > BTW most Unraid users don‘t have a GitHub account. For another test, commenting the crashing instructions in this archive [CoreFreq_Goldmont.tar.gz](https://github.com/cyring/CoreFreq/files/14361584/CoreFreq_Goldmont.tar.gz)