Colin Schmidt

Hmm I got a bunch of these errors: ``` ======== Starting Transform CheckWidths$ ======== [error] (run-main-0) firrtl.passes.PassExceptions: [error] firrtl.passes.CheckWidths$TailWidthException: @[Decoupled.scala 221:40:[email protected]]: [module FinishQueue] Parameter 1 in tail operator is larger...

So there are two methods to register and extension, via the ISA string and via the `--extension` parameter. From my reading of the current code using the ISA string will...

In person discussion notes: Yes this is a reasonable constraint that we probably haven't encountered before because most compilers support a more reasonable minimum size such that anything smaller should...

Thanks for creating the issue. I started working on some of this and hope to have it done over the weekend.

Let's just merge your branch. I have the scala style directory and build.sbt but the pfpmp contents, so I can just base my changes on yours.

Yeah thats a good point. The GenerateTop and GenerateHarness need to be ordered to achieve the desired affect. I guess we'll need another firrtl feature request @azidar :)

We will need to track https://github.com/ucb-bar/firrtl/issues/446 for ordering firrtl passes via annotations.

Feature request for clock list: Ensure that the enq data and enq clock have the same clock. I.e. follow the data back to its most recent register and ensure this...

The recent merge added a new submodule `barstools` that you may not have initialized. Please try that with: `git submodule update --init --recursive barstools`

The benchmarks take many millions of cycles and each cycle prints at least 100 characters, so >1GB isn't unreasonable. They can be run without printing that log, see the `run-asm-tests-fast`...