ucb-bar
Pad TODO
Single Pad annotation per component with concatenated strings for sub-annotations. Check that top-level pin gets added to the right metal layer (esp for analog, which is single-ported -- need to make sure pad is actually hooked up properly).
Clk pass TODO:
Check: CreateClkConstraints ClkDivider ClkGenSpec
Need to propagate srcs through clk mux (pg. 66) top mod clk sink -> create clk mod clk source -> create / gen ; if gen, gen from sink's source
generate tcl clkname = module name_id pll is not generated clk -> async to all top clk src top clk srcs should be async if no relation is specified if async already specified (lhs, rhs) = (lhs, rhs) or (rhs, lhs) then don't include top mod input clks should create clk
yaml: name, clk, reset, reg, etc. pin name if not black box --> need to change clk src to reg or mux foundry thing (w/ lib) -- size_only; does inline instance work on un-inlined instance?
make differential clk div (+ test) make clk mux (+ test) try new clkdiv with diff params -- make sure uniquness
double check refedge for derived clk of gen2 check mem works with multiclk
Feature request for clock list:
Ensure that the enq data and enq clock have the same clock. I.e. follow the data back to its most recent register and ensure this clock is the same as the enq clock.
Just hit a bug like this in RTL
Add different flavors of LUTs (see the ones used by FFT) Mixed Radix (add, counters) -- in dsptools?