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Make CheckWidths accept zero-width UIntLiterals

Open jackkoenig opened this issue 8 years ago • 12 comments

Fixes #508

Release notes: Zero-width literals with value zero are now allowed.

jackkoenig avatar Apr 07 '17 21:04 jackkoenig

This change seems to lead to a zero-width Vec issue in the Chisel tests. Looking into it

jackkoenig avatar Apr 07 '17 21:04 jackkoenig

(Well I think this one combined with the one where Chisel emits zero width UInts)

jackkoenig avatar Apr 07 '17 21:04 jackkoenig

@colinschmidt Can you confirm this works?

donggyukim avatar Apr 07 '17 22:04 donggyukim

Here's the Chisel branch, looking in to the Chisel test failure: https://github.com/ucb-bar/chisel3/tree/one-entry-enum

jackkoenig avatar Apr 07 '17 22:04 jackkoenig

Thanks @jackkoenig I'll test with that branch and this firrtl branch

colinschmidt avatar Apr 07 '17 22:04 colinschmidt

Hmm I got a bunch of these errors:

======== Starting Transform CheckWidths$ ========
[error] (run-main-0) firrtl.passes.PassExceptions:
[error] firrtl.passes.CheckWidths$TailWidthException:  @[Decoupled.scala 221:40:[email protected]]: [module FinishQueue] Parameter 1 in tail operator is larger than input width 1.
[error] firrtl.passes.CheckWidths$TailWidthException:  @[Decoupled.scala 221:40:[email protected]]: [module FinishQueue_1] Parameter 1 in tail operator is larger than input width 1.
[error] firrtl.passes.CheckWidths$TailWidthException:  @[Decoupled.scala 221:40:[email protected]]: [module FinishQueue_2] Parameter 1 in tail operator is larger than input width 1.
[error] firrtl.passes.CheckWidths$TailWidthException:  @[Decoupled.scala 221:40:[email protected]]: [module Queue_16] Parameter 1 in tail operator is larger than input width 1.
[error] firrtl.passes.CheckWidths$TailWidthException:  @[Decoupled.scala 221:40:[email protected]]: [module Queue_17] Parameter 1 in tail operator is larger than input width 1.
[error] firrtl.passes.CheckWidths$TailWidthException:  @[Decoupled.scala 221:40:[email protected]]: [module Queue_127] Parameter 1 in tail operator is larger than input width 1.

colinschmidt avatar Apr 07 '17 22:04 colinschmidt

It seems like there might be some hidden zero-width wire problems in Firrtl, perhaps we should just patch Chisel by not emitting zero-width for 1-entry Enums and at least fix THAT problem

jackkoenig avatar Apr 07 '17 22:04 jackkoenig

I added a testcase that currently fails so that a fix for it (and possibly other issues) can accompany this change.

jackkoenig avatar Apr 07 '17 23:04 jackkoenig

Any updates on this? Is this dated?

azidar avatar Nov 21 '18 22:11 azidar

No updates, I think it's a lingering problem

jackkoenig avatar Nov 21 '18 22:11 jackkoenig

All tests (FIRRTL) currently pass. I'm running regression tests with the rest of the BIG6.

ucbjrl avatar Jan 08 '19 22:01 ucbjrl

I rebased and cleaned up. The previously failing Vec test works now; should we consider merging this now @jackkoenig?

albert-magyar avatar Apr 14 '20 00:04 albert-magyar