Colin Schmidt

Currently custom RTL(`CUSTOM_VLOG`) only work for VLSI synthesis and place and route, but if you try to use it to simulate or do power analysis it will fail. It would...

vcs arguments not properly ignored by fesvr

9

A fresh clone of rocket-chip with riscv-tools built from the submodule pointer can not run assembly tests in the vsim directory. The extra vcs arguments are no longer correctly ignored...

Bulk connects do not override bundle components

4

This code behaves differently in Chisel2 and 3. It would be good if the compatibility checker would catch it. ``` io.rocc.resp.ready := !(wb_reg_valid && wb_ctrl.wxd) ... csr.io.rocc io.rocc ``` In...

Grouping Transform Example

1

An example of how to use the grouping transform for something like a cluster of cores would be good. _Originally posted by @colinschmidt in https://github.com/ucb-bar/chipyard/pull/446_

ignore arguments that start with +

2

This causes htif to skip unknown arguments that start with `+`. Other arguments that start with `-` will still issue stderr messages but not stop option parsing. This is an...

Related to #58 In rocket-chip land things that drive ResetCatchAndSync and the like could be emitted as HammerIR timing constraints. This is a common source of timing problems in phys...

Should make #50 nicer

As a command line option you should be able to tell it how big a memory needs to be in bits before it becomes an SRAM. If the memory is...

If you have memories that need mapping and ask to not use syn-flops MacroCompiler should error and inform you that it found no library memories in your input mdf/json.

The following code produces sub-optimal code: ``` extern void f(void); void f2(int test) { switch (test) { case 1: f(); break; case 2: f(); break; case 3: f(); break; case...