chisel

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Fix empty aggregate width

2

Split out focused fix from https://github.com/chipsalliance/chisel/pull/3344#discussion_r1227398218 ### Contributor Checklist - [ ] Did you add Scaladoc to every public function/method? - [x] Did you add at least one test demonstrating...

jackkoenig

This is an automatic backport of pull request #3352 done by [Mergify](https://mergify.com). Cherry-pick of b910bf94600a67f36a401e5ee85ec5c7426da348 has failed: ``` On branch mergify/bp/3.6.x/pr-3352 Your branch is up to date with 'origin/3.6.x'. You...

mergify[bot]

This is an automatic backport of pull request #3349 done by [Mergify](https://mergify.com). Cherry-pick of 951f8b7cc688f6b49ab9b3461a9911d28f300fc4 has failed: ``` On branch mergify/bp/3.6.x/pr-3349 Your branch is up to date with 'origin/3.6.x'. You...

mergify[bot]

Update sbt-scoverage to 2.0.7

2

Updates [org.scoverage:sbt-scoverage](https://github.com/scoverage/sbt-scoverage) from 1.9.3 to 2.0.7. [GitHub Release Notes](https://github.com/scoverage/sbt-scoverage/releases/tag/v2.0.7) - [Version Diff](https://github.com/scoverage/sbt-scoverage/compare/v1.9.3...v2.0.7) I'll automatically update this PR to resolve conflicts as long as you don't change it yourself. If you'd...

scala-steward

I found a few broken links on the docs. Here is a diff identifying what I think should be fixes for them. (In the case of one, removing it entirely)....

mmaloney-sf

**Type of issue**: Feature Request **Is your feature request related to a problem? Please describe.** `svsim` currently makes a "best attempt" to provide the required functionality for recent versions of...

GeorgeLyon

**Type of issue**: Feature Request **Is your feature request related to a problem? Please describe.** Not a problem. But it is slow for Chisel elaborate a large design. **Describe the...

davidmlw

**Type of issue**: Bug Report **Please provide the steps to reproduce the problem:** After clone the chisel package from git through cmd.exe and finishes submodule init and update, I tried...

fangrouli

MixedVecInit should handle signals with bi-directions like VecInit

1

**Type of issue**: Feature Request (It is also a bug report) **Is your feature request related to a problem? Please describe.** If I use `MixedVecInit` with multiple bidirectional bundles such...

zhutmost

Mixed-masked/unmasked-port ReadSyncMem is generated incorrectly when "--repl-seq-mem"

10

**Type of issue**: Bug Report **Please provide the steps to reproduce the problem:** I have attached two write ports to a `ReadSyncMem`. One write port has a mask, and the...

zhutmost