MixedVecInit should handle signals with bi-directions like VecInit

[zhutmost]

Type of issue: Feature Request (It is also a bug report)

Is your feature request related to a problem? Please describe.

If I use MixedVecInit with multiple bidirectional bundles such as DecoupledIO, it will erase the original directions, and cause bugs.

val a1 = IO(Decoupled(UInt(2.W)))
val b2 = IO(Decoupled(UInt(2.W)))
val m1 = MixedVecInit(a1, b2) // bugs
val m2 = VecInit(a1, b2) // correct

In MixedVecInit.apply(elt), chisel developers just use a := b to assign signals. So if elt is a Bundle with both Input and Output directions, some signals won't be connected correctly.

Describe the solution you'd like A clear and concise description of what you want to happen.

MixedVecInit.apply(..) should have a similar implementation like VecInit (see the following figure).

Describe alternatives you've considered A clear and concise description of any alternative solutions or features you've considered.

Additional context Include detailed explanation, stacktraces, related issues, suggestions how to fix, links for us to have context, eg. Stack Overflow, gitter, Scastie.

What is the use case for implementing this feature?

Included in the above code snippet.

[zhutmost]

Just changing https://github.com/chipsalliance/chisel/blob/0c5fccd4c19edf4c5c86643715d4083082c8d43d/src/main/scala/chisel3/util/MixedVec.scala#L31 to

a <> b

maybe can solve the bug? (I haven't tested it).