calyx

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Combinational loops created when `invoke`d component has single group in control sequence

8

I _think_ the title describes what is happening, but I'm not sure. Any input people have is appreciated! I’ve tried to pin down where some combinational loops are being generated...

nathanielnrn

**NOTE: I'm planning to keep this a draft PR until we merge @pedropontesgarcia 's changes making the profiler a standalone tool! Nevertheless, some early eyes on this would be very...

ayakayorihiro

Here's a quick attempt to convert all the low-hanging fruit I could find in the docs to refer to fud2 instead of fud. I haven't done anything about the actual...

sampsyo

[fud2] Low level Rhai documentation

2

I separated out the Rhai API documentation to a new file and wrote some documentation for the low level Rhai API! Would appreciate any thoughts :)

ayakayorihiro

[Fud 2] Migration Tracker

1

Big list of things we need to do to migrate everything over to Fud 2 and fully deprecate Fud 1. Required changes - [ ] Test Suite - [x] `vcd_json`...

EclecticGriffin

Bumps [brace-expansion](https://github.com/juliangruber/brace-expansion) from 1.1.11 to 1.1.12. Release notes Sourced from brace-expansion's releases. v1.1.12 pkg: publish on tag 1.x c460dbd fmt ccb8ac6 Fix potential ReDoS Vulnerability or Inefficient Regular Expression (#65)...

dependabot[bot]

(not ready to be merged) This is an attempt at a simple common subexpression elimination optimization. The rough documentation on how it works is [here](https://docs.google.com/document/d/1X1RS0KP_qpvqX3qL2ph4fV9q-2MZrtbCZVpJtyAjjLs/edit?usp=sharing)

AyanaAlemayehu

`group2seq` can make programs slower

1

I ran into an interesting phenomenon with the `group2seq` pass when running the profiler pass (`validation --> compile-invoke --> profiler-instrumentation --> pre-opt ...`) on some sample programs. It turns out...

ayakayorihiro

[fud2] Synchronous Guarded Assignment Check on Combinational Component

1

I have a couple of guarded assignments ``` WBSel = eq_load.out ? 2'b00; // Loads WBSel = (eq_jal.out | eq_jalr.out) ? 2'b10; // jal, jalr WBSel = !(eq_jal.out | eq_jalr.out)...

elamdf

[primitives] `std_bit_slice` semantics

1

(Feel free to reassign this, not sure which tag is suitable) I was trying to invoke verilator manually on a calyx-generated verilog file and got some warnings of the format...

elamdf