calyx
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calyxir
Intermediate Language (IL) for Hardware Accelerator Generators
This pull request has two contributions. 1. As #2292 mentioned, some ops are combinational but are not marked in Python is_comb() function. 2. Fixed bugs in std_bit_slice verilog template and...
When using the Verilog backend, the primitives aren't included in the output when writing to a file rather than standard out. This is because the file is truncated when it's...
This PR removes ops from `lib.rs` which are duplicated in Rhai scripts.
## Overview At a high level, our [Shared Testing Harness](https://docs.calyxir.org/frontends/queues.html#shared-testing-harness) works by processing a workload of pushes and pops as quickly as possible. **Benefits** of the current setup. - There's...
## Idea ## Here's the[ initial discussion on Zulip](https://calyx.zulipchat.com/#narrow/stream/445268-calyx-opt/topic/First.20Class.20FSMs.20.28.2B.20the.20discussions.20that.20led.20here.29/near/473006448), which touches on the motivation for this. The idea is to be able to instantiate FSMs as a `group`-like construct in...
At the highest level this PR should allow for correct `xclbin`s to be produced from Calyx programs. Broadly speaking this PR does 2 things (sorry for combining them, but some...
The papercut pass detects common problems that are not necessarily an issue and people keep tripping into cases where it is generating false positives. Let's change the default behavior to...
Attempt to close #2253. Still a WiP.
Similar to duplication, the goal with splitting a `seq` block is ultimately to reduce fanout from the one register that normally controls a sequential schedule. Initially, we tried to transform:...