[fud2] Synchronous Guarded Assignment Check on Combinational Component

[elamdf]

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I have a couple of guarded assignments

    WBSel = eq_load.out ? 2'b00;  // Loads
    WBSel = (eq_jal.out | eq_jalr.out) ? 2'b10; // jal, jalr
    WBSel = !(eq_jal.out | eq_jalr.out) & !eq_load.out ? 2'b01;

inside of a comb component comb component WBSel(opcodeMWB: 7) -> (WBSel: 2), which in fud2 <path>.futil -o cpu.sv --to verilog leads to the emitted module containing

always_ff @(posedge clk) begin
  if(~$onehot0({_guard11, _guard8, _guard7})) begin
    $fatal(2, "Multiple assignment to port `_this.WBSel'.");
end

This is an issue, since the module does not have a clock (it is combinational), and verilator (rightly) refuses to compile it.

fud emits

always_comb begin
  if(~$onehot0({_guard11, _guard8, _guard7})) begin
    $fatal(2, "Multiple assignment to port `_this.WBSel'.");
end

which seems more reasonable.