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calyxir
Intermediate Language (IL) for Hardware Accelerator Generators
This is a bookmark for a change that we'd like to make across all our queues. I'm parking it here because two big changes to the queues, https://github.com/calyxir/calyx/issues/2067 and https://github.com/calyxir/calyx/issues/1810,...
I run into this issue a bunch when I'm running runt tests and kill the execution with CTRL-C since doing so leaves all the work directories lying around. I am...
The Synthesis Papercut pass [incorrectly flags](https://github.com/calyxir/calyx/blob/6f895a1353020ce254860c3aa0fcfa2ba1abf4c4/calyx-opt/src/passes/synthesis_papercut.rs#L77) reference memories that are only read or written to as needing `@external` flags. This happens because the pass does not recognize that reference memories...
As #2131 explains, it is a bad idea to create a group like so: ``` with comp.group("big_group") as big_group: ... foo.in_ = ... bar.in_ = ... ... big_group.done = (foo.done...
This issue is a summary of this [slack thread](https://cucapra.slack.com/archives/CLLM75W4R/p1718141857620339). Suppose I made the following combinational group: ``` comb group check { lt_1.left = reg_1.out; lt_1.right = reg_2.out; lt_2.left = reg_3.out;...
#2085 introduces the possibility to pass in subtypes of components as part of `invokes.` The `well_formedness` pass currently designates a component `a` as a subtype of `b` if `a` has...
This issue is about divergent behavior between `icarus-verilog`, `verilator`, and the Calyx interpreter. Here's a toy eDSL program and it's associated data file: ``` # bug.py import calyx.builder as cb...
This is a tracking issue for an effort to switch Calyx's testbenching. ## Background Currently, all Calyx-compiled Verilog programs use the same [standalone testbench](https://github.com/calyxir/calyx/blob/main/fud2/rsrc/tb.sv). The downside of this setup is...
Currently the read-compute-write AXI generator only creates a [single set of channels](https://github.com/calyxir/calyx/blob/main/yxi/axi-calyx/axi-generator.py#L658-L667) for the first `seq_mem` in a Calyx program, as opposed to an individual channel for each memory. This...
Fud currently depends on `calyx-py`, our eDSL. Let's try to tease those two apart. When done, let's update the [docs](https://docs.calyxir.org/#installing-the-command-line-driver).