[fud2] Switch to custom testbench generation

[ayakayorihiro]

This is a tracking issue for an effort to switch Calyx's testbenching.

Background

Currently, all Calyx-compiled Verilog programs use the same standalone testbench. The downside of this setup is that Calyx's Verilog backend needs to generate code for setting up memories (readmemh/writememh/etc), and other potential routes of obtaining Verilog (like FIRRTL) may not be able to do this. (We also want to separate out the memory initialization to the testbench, since the design itself should be independent of memory loading/writing) As part of the FIRRTL backend effort, we've created a rig that makes a custom testbench for each Calyx program. fud2 uses this custom testbench rig whenever the FIRRTL backend is involved, but it'll be great if we can make a Calyx-wide switch to using a custom testbench!

Issues and TODOs

• [ ] Simulation using the custom testbench take more cycles than using the standalone testbench (https://github.com/calyxir/calyx/issues/1956)
• [ ] The YXI backend does not emit memory information for ref cells (https://github.com/calyxir/calyx/issues/1993)
  • [x] Edited: Use the external-to-ref pass instead of a sed in fud2.
• [ ] I've introduced lots of states/transitions to the fud2 graph, so we may want the custom testbench to replace the standalone testbench.

Once the above is done, we should have a larger switch to always using the custom testbench.

• [ ] The YXI backend should be built by default.
• [ ] We should deprecate @external.
• [ ] The Verilog backend should always be in "synthesis" mode (don't produce readmemh/writememh)