algrobman

this was my point that from CPU pipe, data transfer point of view other size than XLEN for CSRs does not make sense. (ex MIP/MIE have most of the upper...

BTW, can somebody enlighten me what is the size for fflags and frm CSRs? So far I've found following CSRs defined as 32 bits: mvendorid mcounteren scounteren mcountinhibit fcsr dcsr

Tim, I would like you to consider to change wording of arrsize constraint in next spec release from: > If aarsize specifies a size larger than the register's actual size,...

yes, I meant CSRs, BTW, my background is PowerPC ...

One more problem may exist too - if an implementation does not support some of the "32 bit" CSRs, what error code should register abstract command return if debugger tries...

Guys, one more question , how should a debugger handle RV64F ? Does openOCD detects FLEN too by trying a FPR reads with different arrsize arguments?

And how is all this handled if misa is not implemented? 2nd question: How/where is the "aarsize" for CSRs defined in openOCD? (like 64 bit MTVEC vs 32 bit DCSR)

> I'm not sure I fully understand the question. I meant, where are the CSRs sizes defined in the openOCD code. (source files). If we define some privet CSRs to...

problem is when I'm regressing I have to wait 10x time for 2% of the tests - outliners, which have a lot of exceptions in them. Or when I enable...