algrobman

I still see this mistake in online documentation

Very interesting : if my ISA : ISA: RV32IMCZicsr_Zifencei_Zba Everything passing, including 3 ZBA tests. if it is ISA: RV32IMCZicsr_Zifencei_Zba_Zbb Getting following ``` ESC[32m INFOESC[0m | ESC[32mInitiating signature checking.ESC[0m ESC[1;31m...

@neelgala, riscof behavior after timeout seems not reasonable - instead of terminating the run with Timeout message, riscof continue to signature comparison stage and fails there with misleading message of...

> The tests need to be compiled twice because the same test cannot be expected to run on both the model and the RTL. The RTL is free to implement...

> Alternatively, debug Verilator, Are you kidding ? I'm not programmer

right now we have: -Wno-WIDTH -Wno-MULTIDRIVEN -Wno-UNOPTFLAT -Wno-STMTDLY to disable some warnings ...

Was VCD dumping changed since verilator 4..?

I see some discrepancy with Xcelium. for following ``` logic[7:0] a=1, dec; always @(posedge clk) begin a = a

Even if I define "a" as bit vector, nothing changes in waves and printing 'a' value at negedge clk . (xcellium starts 'a' as 1 , verilator as 0 ,...

BTW, to my original complain about no warnings for operations with X, Z. It's strange that the verilator 5.. started complain about # delays in the code, and does not...