algrobman

the jtag_id input can be tied to any value, including 0, not sure why the change is needed. ..

a) I don't see enough justification of this change in the discussion. There is no many gates will be saved b) SOC with multiple different RISCV cores may need a...

> From IEEE Std 1149.1™-2013 (section 12.1.1), IDCODE bit 0 is required to be 1, so using a 0 value would not be a legal solution. Exactly - this may...

How do verilator version earlier than 5.000 work with latest UVM TB additions to this data base?

VERILATOR is a simulator automatic define, predefined by Verilator

just add +define+TECH_RV_ICG= to synthesis or compilation command Or patch this define in generated common_defines.h

Verilator simulations won't compile with enabled assertions ... On Wednesday, February 22, 2023 at 07:51:01 AM CST, Maciej Kurc ***@***.***> wrote: The output is as intended, here is a fragment:...

BTW, you guys could use pd_defines.vh file for synthesis flow, instead of common_defines.vh, which is also generated and contains just this : ``` `include "common_defines.vh" `undef RV_ASSERT_ON `define RV_PHYSICAL 1...

these were meant to "bungle" independent wires to reduce code typing . they are instantiating dual flop synchronizer modules, which can be replaced by a physical library cell.

there is a simple way to replace synchronizers with special cells: you can redefine rvsyncss module to instantiate specialized synchronizer cells in design/libs/beh_lib.sv or have it's description in separate module...